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TDA9897; TDA9898
Multistandard hybrid IF processing
Rev. 04 -- 25 May 2009 Product data sheet
1. General description
The Integrated Circuit (IC) is suitable for Intermediate Frequency (IF) processing including global multistandard Analog TV (ATV), Digital Video Broadcast (DVB) and mono FM radio using only 1 IC and 1 to 3 fixed Surface Acoustic Waves (SAWs) (application dependent). TDA9898 includes, TDA9897 excludes L and L-accent standard.
2. Features
2.1 General
I I I I I 5 V supply voltage I2C-bus control over all functions Four I2C-bus addresses provided; selection by programmable Module Address (MAD) Three I2C-bus voltage level supported; selection via pin BVS Separate gain controlled amplifiers with input selector and conversion for incoming IF [analog Vision IF (VIF) or Sound IF (SIF) or Digital TV (DTV)] allows the use of different filter shapes and bandwidths All conventional ATV standards applicable by using DTV bandwidth window (SAW) filter Two 4 MHz reference frequency stages; the first one operates as crystal oscillator, the second one as external signal input Stabilizer circuit for ripple rejection and to achieve constant output signals Smallest size, simplest application ElectroStatic Discharge (ESD) protection for all pins
I I I I I
2.2 Analog TV processing
I Gain controlled wideband VIF amplifier; AC-coupled I Multistandard true synchronous demodulation with active carrier regeneration: very linear demodulation, good intermodulation figures, reduced harmonics and excellent pulse response I Integrated Nyquist processing, providing additionally image suppression for high adjacent channel selectivity I Optional use of conventional Nyquist filter to support a wide range of applications I Gated phase detector for L and L-accent standards I Fully integrated VIF Voltage-Controlled Oscillator (VCO), alignment-free, frequencies switchable for all negative and positive modulated standards via I2C-bus I VIF Automatic Gain Control (AGC) detector for gain control; operating as a peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
I Optimized AGC modes for negative modulation; e.g. very fast reaction time for VIF and SIF I Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit Digital-to-Analog Converter (DAC); AFC bits can be read-out via I2C-bus I High precise Tuner AGC (TAGC) TakeOver Point (TOP) for negative modulated standards; TOP adjust via I2C-bus I TAGC TOP for positive standards and Received Signal Strength Indication (RSSI); adjustable via I2C-bus or alternatively by potentiometer I Fully integrated Sound Carrier (SC) trap for any ATV standard (SC at 4.5 MHz, 5.5 MHz, 6.0 MHz and 6.5 MHz) I SIF AGC for gain controlled SIF amplifier and high-performance single-reference Quasi Split Sound (QSS) mixer I Fully integrated sound BP filter supporting any ATV standard I Optional use of external FM or AM sound BP filter I AM sound demodulation for L and L-accent standard I Alignment-free selective FM Phase-Locked Loop (PLL) demodulator with high linearity and low noise; external FM input I Port function I VIF AGC voltage monitor output or port function I TAGC voltage monitor output or port function I VIF AFC current or tuner, VIF, SIF or FM AGC voltage monitor output I 2nd SIF output, gain controlled by internal SIF AGC or by internal FM carrier AGC for Digital Signal Processor (DSP) I Fully integrated BP filter for 2nd SIF at 4.5 MHz, 5.5 MHz, 6.0 MHz or 6.5 MHz
2.3 Digital TV processing
I I I I I I I I I I I I Applicable for terrestrial and cable TV reception 70 dB variable gain wideband IF amplifier (AC-coupled) Gain control via external control voltage (0 V to 3 V) 2 V (p-p) differential low IF (downconverted) output or 1 V (p-p) 1st IF output for direct Analog-to-Digital Converter (ADC) interfacing DVB downconversion with integrated selectivity for Low IF (LIF) Integrated anti-aliasing tracking low-pass filter Fully integrated synthesizer controlled oscillator with excellent phase noise performance Synthesizer frequencies for a wide range of world wide DVB standards (for IF center frequencies of e.g. 34.5 MHz, 36 MHz, 44 MHz and 57 MHz) TAGC detector for independent tuner gain control loop applications TAGC operating as peak detector, fast reaction time due to additional speed-up detector Port function TAGC voltage monitor output
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
2 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
2.4 FM radio mode
I I I I I I I I Gain controlled wideband Radio IF (RIF) amplifier; AC-coupled Buffered RIF amplifier wideband output, gain controlled by internal RIF AGC Use of external FM sound BP filter 2nd RIF output, gain controlled by internal RIF AGC or by internal FM carrier AGC for DSP Alignment-free selective FM PLL demodulator with high linearity and low noise Precise fully digital AFC detector with 4-bit DAC; AFC bits read-out via I2C-bus Port function Radio AFC or tuner, RIF or FM AGC voltage monitor output
3. Applications
I Analog and digital TV front-end applications for TV sets, recording applications and personal computer cards
4. Quick reference data
Table 1. Quick reference data VP = 5 V; Tamb = 25 C. Symbol VP IP Parameter supply voltage supply current ATV QSS; B/G standard; sound carrier trap on; sound BP on Conditions
[1]
Min 4.5 -
Typ 5.0 -
Max 5.5 175
Unit V mA
Analog TV signal processing Video part Vi(IF)(RMS) GVIF(cr) fVIF fVIF(dah) RMS IF input voltage control range VIF gain VIF frequency digital acquisition help VIF frequency window see Table 24 related to fVIF all standards except M/N M/N standard Vo(video)(p-p) peak-to-peak video output voltage positive or negative modulation; normal mode and sound carrier on; W6[1] = 0; W4[7] = 0; W7[4] = 0; see Figure 10 1.7 2.3 1.8 2.0 2.3 MHz MHz V lower limit at -1 dB video output signal 60 60 66 100 V dB MHz
Gdif
differential gain
"ITU-T J.63 line 330"
B/G standard L standard
[2][3]
[2][3]
2 2
5 7 4 4
% % deg deg
dif
differential phase
"ITU-T J.63 line 330"
B/G standard L standard
-
TDA9897_TDA9898_4
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Product data sheet
Rev. 04 -- 25 May 2009
3 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 1. Quick reference data ...continued VP = 5 V; Tamb = 25 C. Symbol Bvideo(-3dB) Parameter -3 dB video bandwidth Conditions trap bypass mode and sound carrier off; AC load: CL < 20 pF, RL > 1 k M/N standard; f = fSC1 = 4.5 MHz; see Figure 21 B/G standard; f = fSC1 = 5.5 MHz; see Figure 23 (S/N)w weighted signal-to-noise ratio normal mode and sound carrier on; B/G standard; 50 % grey video signal; unified weighting filter ("ITU-T J.61"); see Figure 20 normal mode and sound carrier on; fripple = 70 Hz; video signal; grey level; positive and negative modulation; see Figure 11 AFC TV mode
[4]
Min 6
Typ 8
Max -
Unit MHz
SC1
first sound carrier attenuation
[4]
38
-
-
dB
[4]
35
-
-
dB
[2][5]
53
57
-
dB
PSRRCVBS
power supply ripple rejection on pin CVBS
[2]
14
20
-
dB
IAFC/fVIF Audio part Vo(AF)(RMS)
change of AFC current with VIF frequency RMS AF output voltage
[6]
0.85
1.05
1.25
A/kHz
FM: QSS mode; 27 kHz FM deviation; 50 s de-emphasis AM: 54 % modulation FM: 50 s de-emphasis; FM deviation: for TV mode 27 kHz and for radio mode 22.5 kHz AM: 54 % modulation; BP on; see Figure 33
430
540
650
mV
400 -
500 0.15
600 0.50
mV %
THD
total harmonic distortion
80
0.5 100
1.0 -
% kHz
f-3dB(AF)
AF cut-off frequency
W3[2] = 0; W3[4] = 0; without de-emphasis; FM window width = 237.5 kHz
(S/N)w(AF)
AF weighted signal-to-noise ratio
"ITU-R BS.468-4"
FM: 27 kHz FM deviation; 50 s de-emphasis; vision carrier unmodulated; FM PLL only AM: BP off 48 56 dB
44 14
50 20
-
dB dB
PSRR
power supply ripple rejection
fripple = 70 Hz; see Figure 11
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
4 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 1. Quick reference data ...continued VP = 5 V; Tamb = 25 C. Symbol Vo(RMS) Parameter RMS output voltage Conditions IF intercarrier single-ended to GND; see Figure 9 and Table 21 B/G standard; SC1 on; SC2 off; internal BP via FM AGC L standard; without modulation; W7[5] = 0; internal BP + 6 dB 90 140 180 mV Min Typ Max Unit
90
140
180
mV
FM sound part
Vi(FM)(RMS) RMS FM input voltage gain controlled operation; W1[1:0] = 10 or W1[1:0] = 11 or W1[1:0] = 01; see Figure 9 AFC radio mode referenced to 27 kHz FM deviation; 50 s de-emphasis; AM: f = 1 kHz; m = 54 %
[6]
2
-
300
mV
IAFC/fRIF AM
change of AFC current with RIF frequency AM suppression
0.85 35
1.05 46
1.25 -
A/kHz dB
Digital TV signal processing Digital direct IF Vo(dif)(p-p) peak-to-peak differential output voltage between pin OUT2A and pin OUT2B W4[7] = 0 W4[7] = 1 GIF(max) GIF(cr) PSRR maximum IF gain control range IF gain power supply ripple rejection residual spurious at nominal differential output voltage dependent on power supply ripple fripple = 70 Hz fripple = 20 kHz Digital low IF Vo(dif)(p-p) GIF(max) GIF(cr) fsynth peak-to-peak differential output voltage maximum IF gain control range IF gain synthesizer frequency see Table 34 and Table 35 between pin OUT1A and pin OUT1B; W4[7] = 0 output peak-to-peak level to input RMS level ratio
[7] [7]
[8]
1.0 0.50 83 66
1.1 0.55 -
V V dB dB
output peak-to-peak level to input RMS level ratio
60
[8] [8]
60 -
60 60 2 89 66 -
-
dB dB V dB dB MHz
[8]
[8]
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
5 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 1. Quick reference data ...continued VP = 5 V; Tamb = 25 C. Symbol n(synth) Parameter synthesizer phase noise Conditions with 4 MHz crystal oscillator reference; fsynth = 31 MHz; fIF = 36 MHz at 1 kHz at 10 kHz at 100 kHz at 1.4 MHz ripple(pb)LIF low IF pass-band ripple 6 MHz bandwidth 7 MHz bandwidth 8 MHz bandwidth stpb image C/N stop-band attenuation image rejection carrier-to-noise ratio 8 MHz band; f = 15.75 MHz -10 MHz to 0 MHz; BP on at fo = 4.9 MHz; Vi(IF) = 10 mV (RMS); see Figure 37 W7[7] = 0 W7[7] = 0; see Figure 34 and Figure 46
[8][9][10] [8] [8] [8] [8]
Min
Typ
Max
Unit
89 89 98 115 30 30 112
99 99 102 119 40 34 118
2.7 2.7 2.7 -
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dB dB dB dB dB dBc/Hz
Reference frequency input from external source fref Vref(RMS) reference frequency RMS reference voltage
[11]
15
4 150
500
MHz mV
[1] [2] [3] [4] [5] [6] [7] [8] [9]
Values of video and sound parameters can be decreased at VP = 4.5 V. AC load; CL < 20 pF and RL > 1 k. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound carrier traps. Condition: luminance range (5 steps) from 0 % to 100 %. Measurement value is based on 4 of 5 steps. The sound carrier trap can be bypassed by setting the I2C-bus bit W2[0] to logic 0; see Table 23. In this way the full composite video spectrum appears at pin CVBS. The video amplitude is reduced to 1.1 V (p-p). Measurement using 200 kHz high-pass filter, 5 MHz low-pass filter and subcarrier notch filter ("ITU-T J.64"). To match the AFC output signal to different tuning systems a current output is provided. The test circuit is given in Figure 19. The AFC steepness can be changed by resistors R1 and R2. With single-ended load for fIF < 45 MHz RL 1 k and CL 5 pF to ground and for fIF = 45 MHz to 60 MHz RL = 1 k and CL 3 pF to ground. This parameter is not tested during production and is only given as application information. Noise level is measured without input signal but AGC adjusted corresponding to the given input level.
[10] Set with AGC nominal output voltage as reference. For C/N measurement switch input signal off. [11] The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum FM deviation, sound trap frequency, LIF band-pass cut-off frequency, as well as the accuracy of the synthesizer.
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
6 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
5. Ordering information
Table 2. Ordering information Package Name TDA9897HL/V3 TDA9897HN/V3 TDA9898HL/V3 TDA9898HN/V3 LQFP48 HVQFN48 LQFP48 HVQFN48 Description plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm Version SOT313-2 SOT619-1 SOT313-2 SOT619-1 Type number
TDA9897_TDA9898_4
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Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
6. Block diagram
SDA 23 SCL 24 i.c. 14 I2C-BUS ADRSEL BVS 25 32 GNDD 22
TDA9898
AGCDIN 36 SIF AGC
FM peak AM average
A B sideband
IF3A IF3B
3 4
SYNTHESIZER Q I SIDEBAND FILTER C D
IF1A IF1B
6 7
VCO Q I VIF PLL NYQUIST FILTER sideband (L-accent) E
IF2A IF2B CIFAGC
9 10 5 45 VIF AGC VIF AFC DECODER I2C-BUS TOPNEG ACQUISITION HELP standard TOP1 TOP2 PEAK AGC TUNER RSSI DETECTOR AND L STANDARD TUNER AGC
i.c.
SOUND CARRIER TRAP
GROUP DELAY EQUALIZER
F
trap reference SYNTHESIZER AND VCO I2C-BUS TOPPOS AND RSSI standard
G H
TAGC
47
J 48 GND n.c. 2, 18, 37 8 CTAGC 11 TOP2 optional tuner AGC TOP for positive modulation and radio signal strength detector onset 13 LFVIF 1 LFSYN2 38 LFSYN1 34 GDS
001aai732
Fig 1.
Block diagram of TDA9898 (continued in Figure 2)
TDA9897_TDA9898_4
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Product data sheet
Rev. 04 -- 25 May 2009
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
4 MHz reference input R(2) EXTERNAL SOUND BAND-PASS FILTER(1) VP 43, 44 SUPPLY GNDA 40, 41 EXTFILO EXTFILI 15 17
+3 dB
R(2)
FREF 46 4 MHz FREQUENCY REFERENCE
OPTXTAL 39
29 A B 30
OUT2A OUT2B
TDA9898
OUTPUT SWITCH
26 27
OUT1A OUT1B
C
BP on/off BAND-PASS FILTER
FM AGC 21 FM SWITCH FM NB PLL EXTFMI
D
20 CDEEM 31 28 CAF AUD
E AM SWITCH
AM DEMODULATOR
33 VIF AGC TAGC SIF AGC FM AGC AFC port port J I2C-bus port 19 LFFM TAGC 42
CVBS
F G H
16 VIF AGC
MPP
12 35
PORT1 PORT2
PORT3
001aai733
(1) Optional. (2) Connect resistor if input or crystal is not used.
Fig 2.
Block diagram of TDA9898 (continued from Figure 1)
TDA9897_TDA9898_4
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Product data sheet
Rev. 04 -- 25 May 2009
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
SDA 23
SCL 24
i.c. 14 I2C-BUS
ADRSEL BVS 25 32
GNDD 22
TDA9897
AGCDIN 36 SIF AGC
FM peak AM average
A B sideband
IF3A IF3B
3 4
SYNTHESIZER Q I SIDEBAND FILTER C D
IF1A IF1B
6 7
VCO Q I VIF PLL NYQUIST FILTER sideband E
IF2A IF2B
9 10 VIF AGC VIF AFC 45 I2C-BUS TOPNEG ACQUISITION HELP standard TOP1 TOP2 PEAK AGC TUNER RSSI DETECTOR AND L STANDARD TUNER AGC
i.c.
DECODER
SOUND CARRIER TRAP
GROUP DELAY EQUALIZER
F
trap reference SYNTHESIZER AND VCO I2C-BUS TOPPOS AND RSSI standard
G H
TAGC
47
J 48 GND n.c. 2, 5, 18, 37 8 CTAGC 11 TOP2 optional tuner AGC TOP for positive modulation and radio signal strength detector onset 13 LFVIF 1 LFSYN2 38 LFSYN1 34 GDS
001aai734
Fig 3.
Block diagram of TDA9897 (continued in Figure 4)
TDA9897_TDA9898_4
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Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
4 MHz reference input R(2) EXTERNAL SOUND BAND-PASS FILTER(1) VP 43, 44 SUPPLY GNDA 40, 41 EXTFILO EXTFILI 15 17
+3 dB
R(2)
FREF 46 4 MHz FREQUENCY REFERENCE
OPTXTAL 39
29 A B 30
OUT2A OUT2B
TDA9897
OUTPUT SWITCH
26 27
OUT1A OUT1B
C BAND-PASS FILTER D
BP on/off
FM AGC 21 FM SWITCH FM NB PLL EXTFMI
20 CDEEM 31 28 CAF AUD
E AM SWITCH
AM DEMODULATOR
33 VIF AGC TAGC SIF AGC FM AGC AFC port port J I2C-bus port 19 LFFM TAGC 42
CVBS
F G H
16 VIF AGC
MPP
12 35
PORT1 PORT2
PORT3
001aai735
(1) Optional. (2) Connect resistor if input or crystal is not used.
Fig 4.
Block diagram of TDA9897 (continued from Figure 3)
TDA9897_TDA9898_4
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Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
7. Pinning information
7.1 Pinning
39 OPTXTAL
38 LFSYN1
42 PORT3
41 GNDA
40 GNDA
47 TAGC
46 FREF
48 GND
LFSYN2 n.c. IF3A IF3B CIFAGC(1) IF1A IF1B CTAGC IF2A
1 2 3 4 5 6 7 8 9
37 n.c. 36 AGCDIN 35 PORT2 34 GDS 33 CVBS 32 BVS 31 AUD 30 OUT2B 29 OUT2A 28 CAF 27 OUT1B 26 OUT1A 25 ADRSEL SCL 24
008aaa150
45 i.c. MPP 16
TDA9897HL TDA9898HL
IF2B 10 TOP2 11 PORT1 12 LFVIF 13 i.c. 14 EXTFILO 15 EXTFILI 17 n.c. 18 LFFM 19 CDEEM 20 EXTFMI 21 GNDD 22 SDA 23
(1) Not connected for TDA9897HL.
Fig 5.
Pin configuration for LQFP48
TDA9897_TDA9898_4
44 VP 43 VP
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Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
39 OPTXTAL
38 LFSYN1
42 PORT3
41 GNDA
40 GNDA
47 TAGC
46 FREF
48 GND
45 i.c.
44 VP
LFSYN2 n.c. IF3A IF3B CIFAGC(1) IF1A IF1B CTAGC IF2A
1 2 3 4 5 6 7 8 9
43 VP
terminal 1 index area
37 n.c. 36 AGCDIN 35 PORT2 34 GDS 33 CVBS 32 BVS 31 AUD 30 OUT2B 29 OUT2A 28 CAF 27 OUT1B 26 OUT1A 25 ADRSEL SCL 24
008aaa151
TDA9897HN TDA9898HN
IF2B 10 TOP2 11 PORT1 12 LFVIF 13 i.c. 14 EXTFILO 15 MPP 16 EXTFILI 17 n.c. 18 LFFM 19 CDEEM 20 EXTFMI 21 GNDD 22 SDA 23
Transparent top view
(1) Not connected for TDA9897HN.
Fig 6.
Pin configuration for HVQFN48
7.2 Pin description
Table 3. Symbol LFSYN2 n.c. IF3A IF3B CIFAGC IF1A IF1B CTAGC IF2A IF2B TOP2 PORT1 LFVIF i.c. EXTFILO Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TOP potentiometer for positive modulated standards and RSSI reference digital port function 1 or VIF AGC monitor output loop filter VIF PLL internally connected; connect to ground output to external filter TAGC capacitor IF symmetrical input 2 for vision or digital TDA9898: IF AGC capacitor; L standard TDA9897: not connected IF symmetrical input 1 for vision or digital Description loop filter synthesizer 2 (conversion synthesizer) not connected IF symmetrical input 3 for sound
TDA9897_TDA9898_4
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Product data sheet
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Multistandard hybrid IF processing
Pin description ...continued Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 audio signal output I2C-bus voltage select composite video signal output additional video group delay select; leave open for default operation[1] digital port function 2 AGC input for DIF amplifier for e.g. input from channel decoder AGC not connected loop filter synthesizer 1 (filter control synthesizer) optional quartz input analog ground analog ground digital port function 3 or TAGC monitor output supply voltage supply voltage internally connected; connect to ground 4 MHz reference input TAGC output ground; plateau connection Direct Current (DC) decoupling capacitor 1st Digital IF (DIF) symmetrical output Description multipurpose pin: VIF AGC or SIF AGC or FM AGC or TAGC or VIF AFC or FM AFC monitor output input from external filter not connected loop filter FM PLL de-emphasis capacitor external FM input digital ground I2C-bus data input and output I2C-bus clock input address select low IF or 2nd sound intercarrier symmetrical output
Table 3. Symbol MPP EXTFILI n.c. LFFM CDEEM EXTFMI GNDD SDA SCL ADRSEL OUT1A OUT1B CAF OUT2A OUT2B AUD BVS CVBS GDS PORT2 AGCDIN n.c. LFSYN1 OPTXTAL GNDA GNDA PORT3 VP VP i.c. FREF TAGC GND
[1]
Recommendation: Leave this pin open or use a capacitor to GND, as shown in the application diagrams in Figure 47, Figure 48 and Figure 49.
TDA9897_TDA9898_4
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Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
8. Functional description
8.1 IF input switch
Different signal bandwidth can be handled by using two signal processing chains with individual gain control. Switch configuration allows independent selection of filter for analog VIF and for analog SIF (used at same time) or DIF. The switch takes into account correct signal selection for TAGC in the event of VIF and DIF signal processing.
8.2 VIF demodulator
ATV demodulation using 6 MHz DVB window (band-pass) filter (for 6 MHz, 7 MHz or 8 MHz channel width). IF frequencies adapted to enable the use of different filter configurations. The Nyquist processing is integrated. The integrated Nyquist processing provides also adjacent channel suppression. Sideband switch supplies selection of lower or upper sideband (e.g. for L-accent). For optional use of standard Nyquist filter the integrated Nyquist processing can be switched off. Equalizer provides optimum pulse response at different standards [e.g. to cope with higher demands for Liquid Crystal Display (LCD) TV]. Integrated sound traps. Sound trap reference independent from received 2nd sound IF (reference taken from integrated reference synthesizer). IF level selection provides an optimum adaptation of the demodulator to high linearity or low noise.
8.3 VIF AGC and tuner AGC
8.3.1 Mode selection of VIF AGC
Peak white AGC for positive modulation mode with adaptation for speed up and black level AGC (using proven system from TDA9886). For negative modulation mode equal response times for increasing or decreasing input level (optimum for amplitude fading) or normal peak AGC or ultra fast peak AGC.
8.3.2 VIF AGC monitor
VIF AGC DC voltage monitor output (with expanded internal characteristic). VIF AGC read out via I2C-bus (for IF level indication) with zero-calibration via TOP setting (TOP setting either via I2C-bus or via TOP potentiometer).
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Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
8.3.3 Tuner AGC
Independent integral tuner gain control loop (not nested with VIF AGC). Integral characteristic provides high control accuracy. Accurate setting of tuner control onset (TOP) for integral tuner gain control loop via I2C-bus. For L standard, TAGC remains VIF AGC nested, as from field experience in the past this narrowband TAGC gives best performance. Thus two switchable TAGC systems for negative/DIF and positive modulation implemented. L standard tuner time constant switching integrated (= speed up function in the event of step into high input levels), to speed up settling time. For TOP setting at L standard, additional adjustment via optional potentiometer or I2C-bus is provided. Tuner AGC status bit provided.
8.4 DIF/SIF FM and AM sound AGC
External AGC control input for DIF. DIF includes direct IF and low IF. Integrated gain control loop for SIF. AGC control for FM SIF related to used SAW bandwidth. Peak AGC control in the event of FM SIF. Ultra fast SIF AGC time constant when VIF AGC set to ultra fast mode. Slow average AGC control in the event of AM sound. AM sound AGC related to AM sound carrier level. Fast AM sound AGC in the event of fast VIF AGC (speed up). SIF/FM AGC DC voltage monitor output with expanded internal characteristic.
8.5 Frequency phase-locked loop for VIF
Basic function as previous TDA9887 design. PLL gating mode for positive and negative modulation, optional. PLL optimized for either overmodulation or strong multipath.
TDA9897_TDA9898_4
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Product data sheet
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NXP Semiconductors
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Multistandard hybrid IF processing
8.6 DIF/SIF converter stage
Frequency conversion with sideband suppression. Selection mode of upper or lower sideband for pass or suppression. Suppression around zero for frequency conversion. Conversion mode selection via synthesizer for DIF and radio mode or via VIF Frequency Phase-Locked Loop (FPLL) for TV QSS sound (FM/AM). External BP filter (e.g. for 4.5 MHz) for additional filtering, optional. Bypass mode selection for use of external filter. Integrated SIF BP tracking filter for chroma suppression. Integrated tracking filters for LIF. Symmetrical output stages for direct IF, LIF and 2nd SIF (intercarrier signal). Second narrowband gain control loop for 2nd SIF via FM PLL.
8.7 Mono sound demodulator
8.7.1 FM PLL narrowband demodulation
Additional external input for either TV or radio intercarrier signal. FM carrier selection independent from VIF trap, because VIF trap uses reference via synthesizer. FM wide and ultra wide mode with adapted loop bandwidth and different selectable FM acquisition window widths to cope with FM overmodulation conditions.
8.7.2 AM sound demodulation
AM sound envelope detector. L and L-accent standard without SAW switching (done by sideband selection of SIF converter).
8.8 Audio amplifier
Different gain settings for FM sound to adapt to different FM deviation. Switchable de-emphasis for FM sound. Automatic mute function when FM PLL is unlocked. Forced mute function. Output amplifier for AM sound.
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Multistandard hybrid IF processing
8.9 Synthesizer
The synthesizer supports SIF/DIF frequency conversion. A large set of synthesizer frequencies in steps of 0.5 MHz enables flexible combination of SAW filter and required conversion frequency. Synthesizer loop internally adapted to divider ratio range for optimum phase noise requirement (loop bandwidth). Synthesizer reference either via 4 MHz crystal or via an external source. Individual pins for crystal and external reference allows optimum interface definition and supports use of custom reference frequency offset.
8.10 I2C-bus transceiver and slave address
Four different I2C-bus device addresses to enable application with multi-IC use. I2C-bus transceiver input ports can handle three different I2C-bus voltages. Read-out functions as TDA9887 plus additional read out of VIF AGC and VIFLOCK, BLCKLEV and TAGC status.
Table 4. Slave address detection Selectable address bit A3 MAD1 MAD2 MAD3 MAD4 0 0 1 1 A0 1 0 1 0 GND VP resistor to GND resistor to VP Pin ADRSEL
Slave address
9. I2C-bus control
Table 5. Slave addresses For MAD activation via pin ADRSEL: see Table 4. Slave address Name MAD1 MAD2 MAD3 MAD4 Value 43h 42h 4Bh 4Ah Bit A6 1 1 1 1 A5 0 0 0 0 A4 0 0 0 0 A3 0 0 1 1 A2 0 0 0 0 A1 1 1 1 1 A0 1 0 1 0
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9.1 Read format
S
BYTE 1 A6 to A0 slave address R/W 1
A
BYTE 2 D7 to D0 data (R1)
A
BYTE 3 D7 to D0 data (R2)
NA
P
from master to slave
from slave to master
S = START condition A = acknowledge NA = not acknowledge P = STOP condition
001aad167
Fig 7. Table 6. 7 AFCWIN Table 7. Bit 7
I2C-bus read format (slave transmits data) R1 - data read register 1 bit allocation 6 BLCKLEV 5 CARRDET 4 AFC4 3 AFC3 2 AFC2 1 AFC1 0 PONR
R1 - data read register 1 bit description Symbol AFCWIN Description AFC window[1] 1 = VCO in 1.6 MHz AFC window[2] 1 = VCO in 0.8 MHz AFC window[3] 0 = VCO out of 1.6 MHz AFC window[2] 0 = VCO out of 0.8 MHz AFC window[3]
6
BLCKLEV
black level detection 1 = black level detected 0 = no black level detected
5
CARRDET FM carrier detection[4] 1 = detection (FM PLL is locked and level is less than 6 dB below gain controlled range of FM AGC) 0 = no detection
4 to 1 0
AFC[4:1] PONR
automatic frequency control; see Table 8 power-on reset 1 = after power-on reset or after supply breakdown 0 = after a successful reading of the status register
[1] [2] [3] [4]
If no IF input is applied, then bit AFCWIN can be logic 1 due to the fact that the VCO is forced to the AFC window border for fast lock-in behavior. All standards except M/N standard. M/N standard. Typical time constant of FM carrier detection is 50 ms. The minimal recommended wait time for read out is 80 ms.
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Table 8. Automatic frequency control bits fnom is the nominal frequency. Bit AFC4 R1[4] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
[1]
f[1] AFC3 R1[3] 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 AFC2 R1[2] 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 AFC1 R1[1] 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (fnom - 187.5 kHz) fnom - 162.5 kHz fnom - 137.5 kHz fnom - 112.5 kHz fnom - 87.5 kHz fnom - 62.5 kHz fnom - 37.5 kHz fnom - 12.5 kHz fnom + 12.5 kHz fnom + 37.5 kHz fnom + 62.5 kHz fnom + 87.5 kHz fnom + 112.5 kHz fnom + 137.5 kHz fnom + 162.5 kHz (fnom + 187.5 kHz)
In ATV mode f means vision intermediate frequency; in radio mode f means radio intermediate frequency.
Table 9. 7 VIFLOCK Table 10. Bit 7
R2 - data read register 2 bit allocation 6 TAGC 5 VAGC5 4 VAGC4 3 VAGC3 2 VAGC2 1 VAGC1 0 VAGC0
R2 - data read register 2 bit description Symbol VIFLOCK Description VIF PLL lock-in detection 1 = VIF PLL is locked 0 = VIF PLL is not locked
6
TAGC
tuner AGC 1 = active 0 = inactive
5 to 0
VAGC[5:0] AGC level detector; VIF AGC in ATV mode, SIF AGC in radio mode and DIF AGC in DTV mode; see Table 11
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AGC bits VAGC4 R2[4] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VAGC3 R2[3] 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VAGC2 R2[2] 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VAGC1 R2[1] 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VAGC0 R2[0] 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Typical VAGC(VIF) (V) 0 (TOP)[1] -0.04 -0.08 -0.12 -0.16 -0.20 -0.24 -0.28 -0.32 -0.36 -0.40 -0.44 -0.48 -0.52 -0.56 -0.60 -0.64 -0.68 -0.72 -0.76 -0.80 -0.84 -0.88 -0.92 -0.96 -1.00 -1.04 -1.08 -1.12 -1.16 -1.20 -1.24 -1.28 -1.32 -1.36 -1.40 -1.44 -1.48 -1.52
(c) NXP B.V. 2009. All rights reserved.
Table 11. Bit VAGC5 R2[5] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
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AGC bits ...continued VAGC4 R2[4] 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAGC3 R2[3] 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VAGC2 R2[2] 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VAGC1 R2[1] 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VAGC0 R2[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Typical VAGC(VIF) (V) -1.56 -1.60 -1.64 -1.68 -1.72 -1.76 -1.80 -1.84 -1.88 -1.92 -1.96 -2.00 -2.04 -2.08 -2.12 -2.16 -2.20 -2.24 -2.28 -2.32 -2.36 -2.40 -2.44 -2.48 -2.52
Table 11. Bit VAGC5 R2[5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[1]
The reference of 0 (TOP) can be adjusted via TOPPOS[4:0] (register W10; see Table 47 and Table 45) or via potentiometer at pin TOP2.
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9.2 Write format
S
BYTE 1 A6 to A0 slave address R/W 0
A
BYTE 2 A7 to A0 subaddress
A
BYTE 3 bits 7 to 0 data 1
A
BYTE n bits 7 to 0 data n
A
P
from master to slave
S = START condition A = acknowledge P = STOP condition
001aad166
from slave to master
Fig 8.
I2C-bus write format (slave receives data)
9.2.1 Subaddress
Table 12. 7 A7 Table 13. Bit 7 to 4 3 to 0 Table 14. Bit A3 0 0 0 0 0 0 0 0 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 A0 0 1 0 1 0 1 0 1 0 1 0 subaddress for register W1 subaddress for register W2 subaddress for register W3 subaddress for register W4 subaddress for register W5 subaddress for register W6 subaddress for register W7 subaddress for register W8 subaddress for register W9 subaddress for register W10 subaddress for register W11 W0 - subaddress register bit allocation 6 A6 5 A5 4 A4 3 A3 2 A2 1 A1 0 A0
W0 - subaddress register bit description Symbol A[7:4] A[3:0] Description has to be set to logic 0 subaddress; see Table 14
Subaddress control bits Mode
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Table 15. I2C-bus write register overview The register setting after power-on is not specified. Register 7 W1[1] W2[2] W3[3] W4[4] W5[5] W6[6] W7[7] W8[8] W9[9] W10[10] W11[11]
[1] [2] [3] [4] [5] [6] [7] [8] [9]
6 STD1 STD4 AMUTE BP FSFREQ0 TAGC0 VAGC AVIDRED
5 STD0 STD3 FMUTE MPPS1 SFREQ5 AGC2 SIFLEVEL MODEP3 TAGCTC OFFSETN
4 TV STD2 FMWIDE0 MPPS0 SFREQ4 AGC1 VIDLEVEL TAGCIN3 TOPNEG4 TOPPOS4 OFFSETP
3 0 SB DEEMT AMMODE SFREQ3 FMWIDE1 PORT1 FORCESP TOPNEG3 TOPPOS3
2 0 PLL DEEM IFIN1 SFREQ2 TWOFLO MODEP1 PORT3 TOPNEG2 TOPPOS2
1 FM GATE AGAIN1 IFIN0 SFREQ1 VIDEO1V7 FILOUTBP PORT2 TOPNEG1 TOPPOS1 VIFIN3
0 EXTFIL TRAP AGAIN0 VIFIN SFREQ0 DIRECT NYQOFF 0 TOPNEG0 TOPPOS0 VIF31875
RADIO MOD RESCAR VIFLEVEL FSFREQ1 TAGC1 EXTFILO FEATURE 0 0
DAGCSLOPE TAGCIS 0
READTAGC XPOTPOS
BLACKAGC GDEQ
See Table 17 for detailed description of W1. See Table 23 for detailed description of W2. See Table 27 for detailed description of W3. See Table 29 for detailed description of W4. See Table 33 for detailed description of W5. See Table 37 for detailed description of W6. See Table 40 for detailed description of W7. See Table 42 for detailed description of W8. See Table 44 for detailed description of W9.
[10] See Table 47 for detailed description of W10. [11] See Table 50 for detailed description of W11.
9.2.2 Description of data bytes
Table 16. 7 RADIO Table 17. Bit 7 W1 - data write register bit allocation 6 STD1 5 STD0 4 TV 3 0 2 0 1 FM 0 EXTFIL
W1 - data write register bit description Symbol RADIO Description FM mode 1 = radio 0 = ATV/DTV
6 and 5 4
STD[1:0] TV
2nd sound IF; see Table 18 and Table 19 TV mode 1 = ATV QSS 0 = DTV; direct IF or LIF; depends on setting of TV mode (W6[0])
3 and 2 1 and 0
-
0 = fixed value
FM and EXTFIL FM and output switching; see Table 21
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Table 18. Intercarrier sound BP and FM PLL frequency select for ATV, QSS mode For description of bit MOD refer to Table 23 and bits FSFREQ[1:0] are described in Table 33. Bit RADIO W1[7] 0 0 0 0 0 MOD W2[7] 1 1 1 1 0 STD1 W1[6] 0 0 1 1 1 STD0 W1[5] 0 1 0 1 1 FSFREQ1 W5[7] X X X X X FSFREQ0 W5[6] X X X X X 4.5 5.5 6.0 6.5 off M/N standard B/G standard I standard D/K standard L/L-accent standard fFMPLL (MHz) Sound BP
Table 19. Intercarrier sound BP and FM PLL frequency select for radio For description of bit MOD refer to Table 23 and bits FSFREQ[1:0] are described in Table 33. Bit RADIO W1[7] 1 1 1 1 MOD W2[7] 1 1 1 1 STD1 W1[6] X X X X STD0 W1[5] X X X X FSFREQ1 W5[7] 0 0 1 1 FSFREQ0 W5[6] 0 1 0 1 4.5 5.5 6.0 6.5 M/N standard B/G standard I standard D/K standard fFMPLL (MHz) Sound BP
Table 20. Intercarrier sound FM PLL frequency select for radio 10.7 MHz For description of bit MOD refer to Table 23 and for BP refer to Table 29. Bit BP W4[6] 0 MOD W2[7] 0 RADIO W1[7] 1 10.7 fFMPLL (MHz)
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Table 21. 2nd intercarrier and sound I/O switching Switch input numbering in accordance with Figure 9. AMMODE MOD W4[3] X X X X 0 0 0 0 1 1 1 1 FM EXTFIL Audio mode Input signal selection Input switch FM AM Signal input input path FM sound 1 2 3 2 AM 1 sound 1 X X 2 AM 2 sound 2 X X 2 X X X X 5 5 5 5 4 5 5 4 internal Signal at OUT1A and OUT1B Output switch Input Signal path 6 internal BP via FM AGC internal BP internal BP internal BP + 6 dB internal BP internal BP external BP internal BP internal BP internal BP external BP Demodulation via internal BP external BP external input internal BP internal BP internal BP internal BP external BP internal BP internal BP external BP Mono sound
W2[7] W1[1] W1[0] 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1
EXTFILI 7 EXTFMI 7 EXTFILI 6 internal internal internal 6 7 7
external BP via FM AGC external BP
EXTFILI 6 EXTFILI 7 internal internal 7 7
EXTFILI 6
BYPASS internal BAND-PASS
output switch 7 6
OUT1A OUT1B
W7.1 = 0
W7.1 = 1
3 dB
external filter output
external filter input
external FM input
FM: input AGC switch amplifier 1 2 3 AM: fixed-gain amplifier
FM PLL input switch 4 5
AM DEMODULATOR
EXTFILI EXTFILO EXTFMI
008aaa145
Fig 9.
Signal path for intercarrier (2nd SIF) processing
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W2 - data write register bit allocation 6 STD4 5 STD3 4 STD2 3 SB 2 PLL 1 GATE 0 TRAP
Table 22. 7 MOD Table 23. Bit 7
W2 - data write register bit description Symbol MOD Description modulation 1 = negative; FM mono sound at ATV 0 = positive; AM mono sound at ATV
6 to 4 3
STD[4:2] SB
vision IF; see Table 24 sideband for sound IF and digital low IF 1 = upper 0 = lower
2 1
PLL GATE
operating modes; see Table 25 PLL gating 1 = on; fPC = fVIF 175 kHz 0 = off
0
TRAP
sound trap 1 = on 0 = bypass
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Vision IF NYQOFF W7[0] X X X X X X X X 0 0 0 0 X 1 0 X X MOD W2[7] X X X X 1 1 1 1 0 0 0 0 0 0 0 0 0 STD4 W2[6] 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 STD3 W2[5] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 STD2 W2[4] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 fVIF (MHz) Sideband in case of TV = 1 W7[0] = 0 (QSS) 38.0 38.375 38.875 39.875 45.75 58.75 46.25 59.25 32.25 32.625 33.125 33.625 31.875 33.9 33.9 35.0 36.0 low low low low low low low low high high high high high high high high
Table 24. Bit VIF31875 W11[0][1] X X X X X X X X 0 0 0 0 1 X 1 1 1
[1]
Register W11 is logical AND protected by bit W8[7]. Therefore it is required to set W8[7] = 1 to enable pass of any W11 bit.
Table 25. Bit MOD W2[7] 0 0 1 1
VIF PLL gating and detector mode Gating and detector mode PLL W2[2] 0 1 0 1 0 % gating in positive modulation mode (W2[1] = 1) 36 % gating in positive modulation mode (W2[1] = 1) mode on; optimized for overmodulation in negative modulation mode; fPC = fVIF 175 kHz mode off; optimized for multipath in negative modulation mode; fPC = fVIF 175 kHz
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W3 - data write register bit allocation 6 AMUTE 5 FMUTE 4 FMWIDE0 3 DEEMT 2 DEEM 1 AGAIN1 0 AGAIN0
Table 26. 7 RESCAR Table 27. Bit 7
W3 - data write register bit description Symbol RESCAR Description video gain correction for residual carrier 1 = 20 % residual carrier 0 = 10 % residual carrier
6
AMUTE
auto mute 1 = on 0 = off
5
FMUTE
forced mute 1 = on 0 = off
4
FMWIDE0
FM window (W6[3] = 0) 1 = 475 kHz; normal FM phase detector steepness 0 = 237.5 kHz; high FM phase detector steepness
3
DEEMT
de-emphasis time 1 = 50 s 0 = 75 s
2
DEEM
de-emphasis 1 = on 0 = off
1 and 0
AGAIN[1:0] audio gain 00 = 0 dB 01 = -6 dB 10 = -12 dB (only for FM mode) 11 = -18 dB (only for FM mode)
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W4 - data write register bit allocation 6 BP 5 MPPS1 4 MPPS0 3 AMMODE 2 IFIN1 1 IFIN0 0 VIFIN
Table 28. 7 VIFLEVEL Table 29. Bit 7
W4 - data write register bit description Symbol Description VIFLEVEL control of internal VIF mixer input level (W1[4] = 1) and OUT1/OUT2 output level; see Table 30 1 = reduced[1] 0 = normal
6
BP
SIF/DIF BP 1 = on (bit W6[0] = 0; see Table 37) 0 = bypass
5 and 4 3
MPPS[1:0] AGC or AFC output; see Table 31 AMMODE AM mode extension; see Table 21 1 = second selection set 0 = first selection set
2 and 1
IFIN[1:0]
DIF/SIF input 00 = IF1A/B input 01 = IF3A/B input 10 = not used 11 = IF2A/B input
0
VIFIN
VIF input (W11[1] = 0) 1 = IF1A/B input 0 = IF2A/B input
[1]
Not recommended in combination with internal video level set to reduced (W7[4] = 1).
Table 30. Bit TV W1[4] 0 0 1 1 1 1
[1] [2]
List of output signals at OUT1 and OUT2 Output signal at DIRECT W6[0] 0 1 X X X X FM W1[1] X X 0 0 1 1 EXTFIL W1[0] X X 0 1 0 1 OUT1A, OUT1B low IF off intercarrier[1] intercarrier[2] intercarrier[2] intercarrier[1] OUT2A, OUT2B off direct IF off off off off
Intercarrier output level based on wideband AGC of SIF amplifier. Intercarrier output level based on narrowband AGC of FM amplifier.
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Output mode at pin MPP for ATV or radio mode Pin MPP output mode RADIO W1[7] X X X 0 1 X MPPS1 W4[5] 0 0 1 1 1 0 MPPS0 W4[4] 0 1 0 1 1 0 gain control voltage of FM PLL gain control voltage of SIF amplifier TAGC monitor voltage AFC current output, VIF PLL AFC current output, radio mode gain control voltage of VIF amplifier
Table 31. Bit VAGC W7[6] 0 0 0 0 0 1 Table 32. 7 FSFREQ1 Table 33. Bit 7 and 6
W5 - data write register bit allocation 6 FSFREQ0 5 SFREQ5 4 SFREQ4 3 SFREQ3 2 SFREQ2 1 SFREQ1 0 SFREQ0
W5 - data write register bit description Symbol Description ATV; sound trap; TV = 1; see Table 16 and Table 17 00 = M/N standard (4.5 MHz) 01 = B/G standard (5.5 MHz) 10 = I standard (6.0 MHz) 11 = D/K and L/L-accent standard (6.5 MHz) DTV (low IF); upper BP cut-off frequency; TV = 0; see Table 16 and Table 17 00 = 7.0 MHz 01 = 8.0 MHz 10 = 9.0 MHz 11 = recommended mode for direct IF; W6[0] = 1 FSFREQ[1:0] DTV filter or sound trap selection for video
5 to 0
SFREQ[5:0]
synthesizer frequencies; see Table 34 and Table 35
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DIF/SIF synthesizer frequencies (using bit TWOFLO = 0) fsynth (MHz) SFREQ4 W5[4] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 SFREQ3 W5[3] 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 SFREQ2 W5[2] 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 SFREQ1 W5[1] 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 SFREQ0 W5[0] 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 22.0 22.5 23.0 23.5 24.0 24.5 25.0 25.5 26.0 26.5 27.0 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5 36.0 36.5 37.0 37.5 38.0 38.5 39.0 39.5 40.0 40.5 41.0
(c) NXP B.V. 2009. All rights reserved.
Table 34. Bit SFREQ5 W5[5] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
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DIF/SIF synthesizer frequencies (using bit TWOFLO = 0) ...continued fsynth (MHz) SFREQ4 W5[4] 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFREQ3 W5[3] 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 SFREQ2 W5[2] 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 SFREQ1 W5[1] 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 SFREQ0 W5[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 41.5 42.0 42.5 43.0 43.5 44.0 44.5 45.0 45.5 46.0 46.5 47.0 47.5 48.0 48.5 49.0 49.5 50.0 50.5 51.0 51.5 52.0 52.5 53.0 53.5
Table 34. Bit SFREQ5 W5[5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 35. Bit SFREQ5 W5[5] 1
DIF/SIF synthesizer frequency for Japan (using bit TWOFLO = 1) fsynth (MHz) SFREQ4 W5[4] 1 SFREQ3 W5[3] 0 SFREQ2 W5[2] 0 SFREQ1 W5[1] 1 SFREQ0 W5[0] 0 57
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W6 - data write register bit allocation 6 TAGC0 5 AGC2 4 AGC1 3 FMWIDE1 2 TWOFLO 1 VIDEO1V7 0 DIRECT
Table 36. 7 TAGC1 Table 37. Bit
W6 - data write register bit description Symbol Description tuner AGC mode[1] 00 = TAGC integral loop mode; all currents off 01 = TAGC integral loop mode; source current off 10 = TAGC integral loop mode 11 = TAGC derived from IF AGC; recommended for positive modulated signals
7 and 6 TAGC[1:0]
5 and 4 AGC[2:1] 3 FMWIDE1
AGC mode and behavior; see Table 38 FM window 1 = 1 MHz 0 = see Table 27 bit FMWIDE0
2
TWOFLO
synthesizer frequency selection 1 = Japan mode (57 MHz) 0 = synthesizer mode
1
VIDEO1V7 video output level selection; sound carrier trap set to on (W2[0] = 1); see Table 22 and Table 23 1 = 1.7 V at CVBS 0 = 2.0 V at CVBS
0
DIRECT
direct IF at DTV mode; TV set to DTV (W1[4] = 0); see Table 16 and Table 17 1 = direct IF output 0 = low IF output
[1]
In TAGC integral loop mode the pin TAGC provides sink and source currents for control. TakeOver Point (TOP) is set via register TOPNEG W9[4:0].
Table 38. Bit MOD W2[7] 0 0 0 0 0 1 1 1 1
AGC mode and behavior FORCESP W8[3] 0 0 0 0 1 X X X X AGC2 W6[5] 0 0 1 1 X 0 0 1 1 AGC1 W6[4] 0 1 0 1 X 0 1 0 1 normal minimum gain normal normal fast normal minimum gain 2nd 2nd fast normal minimum gain normal fast fast normal minimum gain normal fast VIF AGC mode SIF AGC mode
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
W7 - data write register bit allocation 6 VAGC 5 4 3 PORT1 2 MODEP1 1 FILOUTBP 0 NYQOFF SIFLEVEL VIDLEVEL
Table 39. 7 EXTFILO Table 40. Bit 7
W7 - data write register bit description Symbol EXTFILO Description mute of output buffer of pin EXTFILO 1 = mute 0 = normal
6 5
VAGC
gain control voltage of VIF amplifier at pin MPP; see Table 31 1 = internal SIF level is reduced by 6 dB (only for AM sound) 0 = internal SIF level is normal
SIFLEVEL SIF level reduction
4
VIDLEVEL video level reduction 1 = internal video level is reduced by 6 dB[1] 0 = internal video level is normal
3
PORT1
output state; port 1 mode selection set to logic output port (W7[2] = 1) 1 = output port is HIGH (external pull-up resistor needed) 0 = output port is LOW
2
MODEP1
port 1 mode selection; pin PORT1 1 = logic output port; level controlled by bit PORT1 (W7[3]) 0 = monitor output of VIF AGC voltage
1
FILOUTBP external filter output signal source; see Figure 9 1 = signal for external filter is obtained behind internal BP filter 0 = signal for external filter is obtained behind SIF mixer
0
NYQOFF
internal Nyquist processing; see Table 24 1 = internal Nyquist processing off[2] 0 = internal Nyquist processing on
[1] [2]
Not recommended in combination with internal IF level set to reduced (W4[7] = 1). At internal Nyquist processing off (W7[0] = 1) it is mandatory to set the internal video level to normal (W7[4] = 0).
TDA9897_TDA9898_4
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Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
W8 - data write register bit allocation 6 AVIDRED 5 MODEP3 4 TAGCIN3 3 FORCESP 2 PORT3 1 PORT2 0 0
Table 41. 7 FEATURE Table 42. Bit 7
W8 - data write register bit description Symbol FEATURE Description feature enable 1 = feature PORT2; PORT3 monitor output of TAGC voltage and data write register W11[7:0] enabled 0 = feature disabled; pin PORT2 and pin PORT3 set to high-ohmic; data write register W11[7:0] = 0000 0000
6
AVIDRED
automatic reduction of internal video level for PC / SC < 11.0 dB 1 = enabled 0 = disabled
5
MODEP3
port 3 mode selection; pin PORT3 1 = logic output port; level controlled by bit PORT3 (W8[2]) 0 = monitor output of TAGC voltage
4
TAGCIN3
TAGC IF input selection; feature enable set to enable (W8[7] = 1) 1 = IF3A and IF3B input 0 = IF1A and IF1B input or IF2A and IF2B input depends on VIF input selection (W4[0])
3
FORCESP VIF AGC and SIF AGC fast mode activation; modulation setting (W2[7] = 0) 1 = forced 0 = automatic; dependent on video level
2
PORT3
output state; feature enable set to enable (W8[7] = 1); port 3 mode selection set to logic output port (W8[5] = 1) 1 = output port is HIGH (external pull-up resistor needed) 0 = output port is LOW
1
PORT2
output state; feature enable set to enable (W8[7] = 1) 1 = output port is HIGH (external pull-up resistor needed) 0 = output port is LOW
0
-
0 = fixed value
TDA9897_TDA9898_4
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Product data sheet
Rev. 04 -- 25 May 2009
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 43. 7
W9 - data write register bit allocation 6 TAGCIS 5 TAGCTC 4 TOPNEG4 3 TOPNEG3 2 TOPNEG2 1 TOPNEG1 0 TOPNEG0
DAGCSLOPE Table 44. Bit 7
W9 - data write register bit description Symbol Description 1 = high voltage for high gain 0 = low voltage for high gain DAGCSLOPE AGCDIN input characteristic; see Figure 44
6
TAGCIS
tuner AGC IF input (TOP1) 1 = inverse to VIF input 0 = aligned to VIF input
5
TAGCTC
tuner AGC charge current (TOP1) 1 = high 0 = normal
4 to 0
TOPNEG[4:0] TOP adjustment for integral loop mode (TOP1); recommended for negative modulation; see Table 45 Tuner takeover point adjustment bits W9[4:0] TOPNEG3 W9[3] 1 : 0 : 0 TOPNEG2 W9[2] 1 : 0 : 0 TOPNEG1 W9[1] 1 : 0 : 0 TOPNEG0 W9[0] 1 : 0 : 0 98.5 typical see Figure 13 79.3[2] see Figure 13 59.6 typical TOP adjustment (dBV)[1]
Table 45. Bit TOPNEG4 W9[4] 1 : 1 : 0
[1] [2]
Average step size is 1.255 dB typical. See Table 53 for parameter tuner takeover point accuracy (acc(set)TOP).
Table 46. 7 0 Table 47. Bit 7 6
W10 - data write register bit allocation 6 READTAGC 5 XPOTPOS 4 TOPPOS4 3 TOPPOS3 2 TOPPOS2 1 TOPPOS1 0 TOPPOS0
W10 - data write register bit description Symbol READTAGC Description 0 = fixed value signal source for TAGC read-out on R2[6] 1 = inverse to used TAGC detector (integral or IF based) 0 = aligned to used TAGC detector (integral or IF based)
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Product data sheet
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Multistandard hybrid IF processing
Table 47. Bit 5
W10 - data write register bit description ...continued Symbol XPOTPOS Description TOP derived from IF AGC via I2C-bus or potentiometer (TOP2) 1 = TOP adjustment by external potentiometer at pin TOP2 0 = see Table 48
4 to 0
TOPPOS[4:0]
TOP adjustment for TAGC derived from IF AGC (TOP2); recommended for positive modulation; see Table 48
Table 48. Bit TOPPOS4 W10[4] 1 : 1 : 0
[1]
Tuner takeover point adjustment bits W10[4:0] TOPPOS3 W10[3] 1 : 0 : 0 TOPPOS2 W10[2] 1 : 0 : 0 TOPPOS1 W10[1] 1 : 0 : 0 TOPPOS0 W10[0] 1 : 0 : 0 99.0 typical see Figure 13 78.5[1] see Figure 13 56.9 typical TOP adjustment (dBV)
See Table 53 for parameter tuner takeover point accuracy (acc(set)TOP2).
Table 49. 7 0 Table 50. Bit 7 and 6 5
W11 - data write register bit allocation 6 0 5 OFFSETN 4 OFFSETP 3 BLACKAGC 2 GDEQ 1 VIFIN3 0 VIF31875
W11 - data write register bit description[1] Symbol OFFSETN Description 0 = fixed value VIF PLL offset sink current (approximately 0.6 A) 1 = enabled (requires W11[4] = 0) 0 = disabled
4
OFFSETP
VIF PLL offset source current (approximately 0.6 A) 1 = enabled (requires W11[5] = 0) 0 = disabled
3
BLACKAGC
black level AGC 1 = disabled 0 = enabled
2
GDEQ
activate group delay equalizer 1 = on (if pin 34 is open-circuit) 1 = off (if pin 34 is connected to ground) 0 = off (if pin 34 is open-circuit) 0 = on (if pin 34 is connected to ground)
1
VIFIN3
VIF input selection 1 = IF3A and IF3B input 0 = IF1A and IF1B input or IF2A and IF2B input depends on VIF input selection (W4[0])
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Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 50. Bit 0
W11 - data write register bit description[1] ...continued Symbol VIF31875 Description VIF frequency selection for global ATV application inclusive DVB-T; see Table 24 1 = 31.875 MHz 0 = 32.250 MHz
[1]
Register W11 is logical AND protected by bit W8[7]. Therefore it is required to set W8[7] = 1 to enable pass of any W11 bit.
10. Limiting values
Table 51. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VP Vn tsc Tstg Tamb Tcase Parameter supply voltage voltage on any other pin short-circuit time storage temperature ambient temperature case temperature TDA9898HL (LQFP48) TDA9898HN (HVQFN48) TDA9897HL (LQFP48) TDA9897HN (HVQFN48) Vesd electrostatic discharge voltage human body model machine model
[1] [2] Class 2 according to JESD22-A114. Class B according to EIA/JESD22-A115.
[1] [2]
Conditions all pins except ground to ground or VP
Min 0 -40 -20 -
Max 5.5 VP 10 +150 +70 105 115 105 115 3000 300
Unit V V s C C C C C C V V
11. Thermal characteristics
Table 52. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient TDA9898HL (LQFP48) TDA9898HN (HVQFN48) TDA9897HL (LQFP48) TDA9897HN (HVQFN48) Rth(j-c) thermal resistance from junction to case TDA9898HL (LQFP48) TDA9898HN (HVQFN48) TDA9897HL (LQFP48) TDA9897HN (HVQFN48) 19 10 19 10 K/W K/W K/W K/W Conditions in free air; 2 layer board 67 48 67 48 K/W K/W K/W K/W Typ Unit
TDA9897_TDA9898_4
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Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
12. Characteristics
12.1 Analog TV signal processing
Table 53. Characteristics VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol Supply; pin VP VP IP supply voltage supply current ATV QSS; B/G standard; sound carrier trap on; sound BP on for start of reset at decreasing supply voltage for end of reset at increasing supply voltage; I2C-bus transmission enable VI Ri(dif) Ci(dif) Vi(IF)(RMS) input voltage differential input resistance differential input capacitance RMS IF input voltage lower limit at -1 dB video output signal upper limit at +1 dB video output signal permissible overload GIF IF gain variation difference between picture and sound carrier; within AGC range; f = 5.5 MHz
[4] [3] [3] [2] [1]
Parameter
Conditions
Min 4.5 -
Typ 5.0 -
Max 5.5 175
Unit V mA
Power-on reset VP(POR) power-on reset supply voltage 2.5 3.0 3.3 3.5 4.4 V V
[2]
VIF amplifier; pins IF1A and IF1B or pins IF2A and IF2B or pins IF3A and IF3B 150 1.95 2 3 60 190 0.7 100 320 V k pF V mV mV dB
GVIF(cr) f-3dB(VIF)l f-3dB(VIF)u VLFVIF fVCO(max) fVIF fVIF(dah)
control range VIF gain lower VIF cut-off frequency upper VIF cut-off frequency demodulator[5] voltage on pin LFVIF (DC) maximum VCO frequency VIF frequency digital acquisition help VIF frequency window fVCO = 2fPC see Table 24 related to fVIF all standards except M/N M/N standard
60 0.9 120 -
66 15 80 140 2.3 1.8
3.6 -
dB MHz MHz V MHz MHz MHz MHz
VIF PLL and true synchronous video
TDA9897_TDA9898_4
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Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol tacq Vlock(min)(RMS) Parameter acquisition time RMS minimum lock-in voltage measured on active IF input pins; maximum IF gain; negative modulation mode W2[7] = 1 and PLL set to overmodulation mode W2[2] = 0 and W2[1] = 0 Conditions
[6]
Min -
Typ 30
Max 30 70
Unit ms V
Tcy(dah) tw(dah) Ipul(acq)VIF KO(VIF) KD(VIF) Ioffset(VIF)
digital acquisition help cycle time digital acquisition help pulse width VIF acquisition pulse current VIF VCO steepness VIF phase detector steepness VIF offset current CVBS[7] positive or negative modulation; W6[1] = 0; see Figure 10 W4[7] = 0; W7[4] = 0 W4[7] = 1; W7[4] = 0 W4[7] = 0; W7[4] = 1 sink or source fVIF / VLFVIF IVPLL / VCO(VIF)
64 21 -1
64 26 33 0
33 +1
s s A MHz/V A/rad A
Video output 2 V; pin Vo(video)(p-p)
Normal mode (sound carrier trap active) and sound carrier on peak-to-peak video output voltage
1.7 1.7 1.7
2.0 2.0 2.0
2.3 2.3 2.3
V V V
Vo(CVBS)
CVBS output voltage difference
difference between L and B/G standard; W3[7] = 0 W4[7] = 0; W7[4] = 0 W4[7] = 1; W7[4] = 0 W4[7] = 0; W7[4] = 1 difference between I and B/G standard; 20 % residual carrier at I standard; W3[7] = 1 W4[7] = 0; W7[4] = 0 W4[7] = 1; W7[4] = 0 W4[7] = 0; W7[4] = 1 -100 -100 -100 2.0 2.33 +100 +100 +100 2.75 mV mV mV -240 -240 -240 +240 +240 +240 mV mV mV
Vvideo/Vsync
video voltage to sync voltage ratio
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol Vsyncl Parameter sync level voltage Conditions W4[7] = 0; W7[4] = 0 W4[7] = 1; W7[4] = 0 W4[7] = 0; W7[4] = 1 Vclip(video)u Vclip(video)l RO Ibias(int) Isink(o)(max) Isource(o)(max) Vo(CVBS) Vblt/VCVBS Vblt(v)/VCVBS upper video clipping voltage lower video clipping voltage output resistance internal bias current (DC) maximum output sink current maximum output source current CVBS output voltage difference black level tilt to CVBS voltage ratio vertical black level tilt to CVBS voltage ratio for emitter-follower AC and DC AC and DC 50 dB gain control 30 dB gain control negative modulation worst case in L standard; vision carrier modulated by test line [Vertical Interval Test Signal (VITS)] only
[3]
Min 1.0 0.9 0.9
Typ 1.2 1.2 1.2
Max 1.4 1.5 1.5 0.9 30 0.5 0.1 1 3
Unit V V V V V mA mA mA dB dB % %
VP - 1.2 VP - 1 1.5 1 3.9 0.4 2.0 -
Gdif
differential gain
"ITU-T J.63 line 330"
B/G standard L standard
[8]
[8]
2 2 57
5 7 4 4 -
% % deg deg dB
dif
differential phase
"ITU-T J.63 line 330"
B/G standard L standard
[9]
(S/N)w
weighted signal-to-noise ratio
B/G standard; 50 % grey video signal; unified weighting filter ("ITU-T J.61"); see Figure 20 M/N standard; 50 IRE grey video signal; see Figure 20 fundamental wave and harmonics
53
(S/N)unw
unweighted signal-to-noise ratio RMS residual picture carrier voltage
47
51
-
dB
VPC(rsd)(RMS) fPC(p-p)
[3]
2 -
5 12
mV kHz
peak-to-peak picture carrier 3 % residual carrier; frequency variation 50 % serration pulses; L standard
-
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
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42 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol Parameter phase difference Conditions 0 % residual carrier; 50 % serration pulses; L standard; L-gating = 0 % AC load: CL < 20 pF, RL > 1 k fripple = 70 Hz; video signal; grey level; positive and negative modulation; see Figure 11 0.5 MHz to 2.5 MHz 2.5 MHz to 3.6 MHz 3.6 MHz to 3.8 MHz 3.8 MHz to 4.2 MHz SC1 SC2 td(grp)CC first sound carrier attenuation second sound carrier attenuation color carrier group delay time f = fSC1 = 4.5 MHz f = fSC1 60 kHz f = fSC2 = 4.724 MHz f = fSC2 60 kHz f = 3.58 MHz; including transmitter pre-correction; see Figure 22 0.5 MHz to 3.2 MHz 3.2 MHz to 4.5 MHz 4.5 MHz to 4.8 MHz 4.8 MHz to 5 MHz SC1 SC2 SC(NICAM) td(grp)CC first sound carrier attenuation second sound carrier attenuation NICAM sound carrier attenuation attenuation color carrier group delay time f = fSC1 = 5.5 MHz f = fSC1 60 kHz f = fSC2 = 5.742 MHz f = fSC2 60 kHz fcar(NICAM) = 5.85 MHz; f = fcar(NICAM) 250 kHz f = f(N+1)ch = 7 MHz f = f(N+1)ch 750 kHz f = 4.43 MHz; including transmitter pre-correction; see Figure 24
[13] [13] [3]
Min -
Typ -
Max 3
Unit %
H(video) sp PSRRCVBS
video harmonics suppression spurious suppression power supply ripple rejection on pin CVBS
[10]
35 40 14
40 20
-
dB dB dB
[11]
M/N standard inclusive Korea; see Figure 21[12] ripple(resp)f frequency response ripple -1.5 -2 -3 -16 38 29 25 16 -75 -50 +1 +1 +1 +1 +75 dB dB dB dB dB dB dB dB ns
B/G standard; see Figure 23[12] ripple(resp)f frequency response ripple -1.5 -3 -5 -12 35 26 25 16 12 21 5 -75 -10 +1 +1 +1 +1 +75 dB dB dB dB dB dB dB dB dB dB dB ns
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
43 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol ripple(resp)f Parameter 25[12] 0.5 MHz to 3.2 MHz 3.2 MHz to 4.5 MHz 4.5 MHz to 5 MHz 5 MHz to 5.5 MHz SC1 SC(NICAM) td(grp)CC first sound carrier attenuation NICAM sound carrier attenuation color carrier group delay time frequency response ripple f = fSC1 = 6.0 MHz f = fSC1 60 kHz fcar(NICAM) = 6.55 MHz; f = fcar(NICAM) 250 kHz f = 4.43 MHz; see Figure 26 0.5 MHz to 3.1 MHz 3.1 MHz to 4.5 MHz 4.5 MHz to 4.8 MHz 4.8 MHz to 5.1 MHz SC1 SC2(us) SC2(ls) SC(NICAM) td(grp)CC first sound carrier attenuation second sound carrier attenuation (upper side) second sound carrier attenuation (lower side) NICAM sound carrier attenuation color carrier group delay time f = fSC1 = 6.5 MHz f = fSC1 60 kHz f = fSC2 = 6.742 MHz f = fSC2 60 kHz f = fSC2 = 6.258 MHz f = fSC2 60 kHz fcar(NICAM) = 5.85 MHz; f = fcar(NICAM) 250 kHz f = 4.28 MHz; including transmitter pre-correction; see Figure 28 0.5 MHz to 3.2 MHz 3.2 MHz to 4.5 MHz 4.5 MHz to 4.8 MHz 4.8 MHz to 5.3 MHz SC(NICAM) SC(AM) td(grp)CC NICAM sound carrier attenuation AM sound carrier attenuation color carrier group delay time fcar(NICAM) = 5.85 MHz; f = fcar(NICAM) 250 kHz f = fSC(AM) = 6.5 MHz f = fSC(AM) 30 kHz f = 4.28 MHz; including transmitter pre-correction; see Figure 30
[13] [13]
Conditions
Min -1.5 -2 -4 -12 35 26 12 -75
Typ -15
Max +1 +1 +1 +1 +75
Unit dB dB dB dB dB dB dB ns
I standard; see Figure
frequency response ripple
D/K standard; see Figure 27[12] ripple(resp)f -1.5 -2 -4 -6 35 26 25 16 25 16 6 -50 0 +1 +1 +1 +1 +100 dB dB dB dB dB dB dB dB dB dB dB ns
L standard; see Figure 29[12] ripple(resp)f frequency response ripple -1.5 -2 -4 -12 5 38 29 -75 -5 +1 +1 +1 +1 +75 dB dB dB dB dB dB dB ns
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
44 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Video output 1.7 V; pin CVBS; see Figure 50, optional CVBS buffer at setting W6[1] = 1 Normal mode (sound carrier trap active) and sound carrier on Vo(video)(p-p) peak-to-peak video output voltage positive or negative modulation; W6[1] = 1; see Figure 10 W4[7] = 0; W7[4] = 0 W4[7] = 1; W7[4] = 0 W4[7] = 0; W7[4] = 1 Vsyncl sync level voltage W4[7] = 0; W7[4] = 0 W4[7] = 1; W7[4] = 0 W4[7] = 0; W7[4] = 1 Video output 1.1 V; pin CVBS Trap bypass mode and sound carrier off[12] Vo(video)(p-p) Vsyncl Vclip(video)u Vclip(video)l Bvideo(-3dB) (S/N)w peak-to-peak video output voltage sync level voltage upper video clipping voltage lower video clipping voltage -3 dB video bandwidth weighted signal-to-noise ratio AC load: CL < 20 pF, RL > 1 k B/G standard; 50 % grey video signal; unified weighting filter ("ITU-T J.61"); see Figure 20 M/N standard; 50 IRE grey video signal; see Figure 20
[9]
1.44 1.44 1.44 1.0 0.9 0.9
1.7 1.7 1.7 1.2 1.2 1.2
1.96 1.96 1.96 1.4 1.5 1.5
V V V V V V
see Figure 10
-
1.1 1.5
0.9 -
V V V V MHz dB
VP - 1.2 VP - 1 6 54 0.4 8 -
(S/N)unw
unweighted signal-to-noise ratio
[9]
47
51
-
dB
VIF AGC Pin MPP Vmonitor(VIFAGC) VAGC VIF AGC monitor voltage AGC voltage see Figure 12; Vi(IF) set to 1 mV (60 dBV) 10 mV (80 dBV) 200 mV (106 dBV) 2.0 2.4 3.0 2.5 3.0 VP V V V
[3]
0.5
-
4.5
V
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
45 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol tresp Parameter response time Conditions increasing VIF step; negative modulation normal mode 2nd mode fast 2nd mode increasing VIF step; positive modulation normal mode fast mode decreasing VIF step; negative modulation normal mode 2nd mode 2nd mode (speed-up) fast 2nd mode fast 2nd mode (speed-up) decreasing VIF step; positive modulation 20 dB normal mode fast mode; W8[3] = 1 fast mode (speed-up) th(fast)VIF VVAGC(step) Pin CIFAGC Ich(max) maximum charge current L standard; normal mode; W8[3] = 0 L standard; fast mode; W8[3] = 1 Ich(add) additional charge current L standard: in the event of missing VITS pulses and no white video content L standard; normal mode; W8[3] = 0 L standard; fast mode; W8[3] = 1 or speed-up 75 100 2.0 100 125 A mA nA VIF fast mode threshold L standard VIF AGC voltage difference see Table 11 (step)
[16] [15] [15] [14] [14] [14]
Min
Typ
Max
Unit
-
100 9 3
-
s/dB s/dB s/dB
-
100 5
-
s/dB s/dB
-
70 250 20 80 6
-
s/dB s/dB s/dB s/dB s/dB
[14]
-10 -
900 180 3 24 -6 40
-2 -
ms ms/dB ms/dB ms/dB dB mV/bit
Idch
discharge current
-
35 1.4
-
nA A
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
46 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Tuner AGC; pin TAGC TAGC integral loop mode (W6[7:6] = 10); TAGC is current output; applicable for negative modulation only; unmodulated VIF; see Table 44 and Figure 13 Vi(IF)(RMS) RMS IF input voltage for TOP1; at starting point of tuner AGC takeover; Isink(TAGC) = 100 A W9[4:0] = 0 0000 W9[4:0] = 1 0000 W9[4:0] = 1 1111 acc(set)TOP1 Isource TOP1 setting accuracy source current TAGC charge current W9[5] = 0 W9[5] = 1 fast mode activated by internal level detector; W9[5] = 0 fast mode activated by internal level detector; W9[5] = 1 Isink sink current TAGC discharge current; VTAGC = 1 V W9[4:0] = 1 0000
[3]
-2 0.20 1.6 7
59.6 78.3 98.5 0.33 2.5 11
+2 0.45 3.4 15
dBV dBV dBV dB A A A
60
90
120
A
375 50
500 0.006 -
625 0.02 0.3 10
A dB/K M V V dB
acc(set)TOP1/T TOP1 setting accuracy variation with temperature RL Vsat(u) Vsat(l) th(fast)AGC load resistance upper saturation voltage lower saturation voltage AGC fast mode threshold
pin operating as current output pin operating as current output activated by internal fast AGC detector; I2C-bus setting corresponds to W9[4:0] = 1 0000 before activating; Vi(IF) below th(fast)AGC
[3]
VP - 0.3 6 8
td
delay time
40
60
80
ms
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
47 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit TAGC loop based on VIF AGC (W6[7:6] = 11); TAGC is voltage output; applicable for TV mode: positive modulation and optional for negative modulation); see Table 47, Figure 13 and Figure 14 Vi(IF)(RMS) RMS IF input voltage for TOP2; at starting point of tuner AGC takeover; VTAGC = 3.5 V RTOP2 = 22 k or W10[5:0] = 00 0000 RTOP2 = 10 k or W10[5:0] = 01 0000 RTOP2 = 0 k W10[5:0] = 01 1111 acc(set)TOP2 TOP2 setting accuracy VTAGC = 3.5 V no tuner gain reduction maximum tuner gain reduction Gslip(TAGC) TAGC slip gain offset tuner gain voltage from 0.6 V to 3.5 V pin open-circuit adjustment of VIF AGC based TAGC loop W10[5] = 1; external resistor operation W10[5] = 0; forced I2C-bus operation Pin CTAGC VCTAGC IL RO voltage on pin CTAGC leakage current output resistance sink or source equivalent time constant resistance
[3] [3] [3]
-8 4.5 0.2 3
56.9 78.5 98 99 0.03 5
+8 0.07 VP 0.6 8
dBV dBV dBV dBV dB dB/K V V dB
acc(set)TOP2/T TOP2 setting accuracy variation with temperature VO output voltage
TOP adjust 2; pin TOP2; IF based TAGC loop mode; see Figure 14 VTOP2 RI RTOP2 voltage on pin TOP2 (DC) input resistance resistance on pin TOP2 3.5 27 V k
0 100
-
22 -
k k
0.2 -
10
0.55VP 10 -
V nA M
Pin MPP output characteristic General Vsat(u) Vsat(l) Io(max) RO upper saturation voltage lower saturation voltage maximum output current output resistance sink or source
[3] [3]
VP - 0.8 VP - 0.5 350 0.5 1.3
0.8 3
V V A k
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
48 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol Gv Parameter voltage gain Conditions voltage on pin MPP to internal control voltage; see Table 31 VIF AGC; see Figure 12 SIF AGC; see Figure 16 FM AGC; see Figure 15 TAGC; see Figure 12 AFC monitor (current output) Io output current sink or source; see Figure 17 and Figure 18 100 kHz VIF deviation 200 kHz VIF deviation 1.5 MHz VIF deviation AFC TV mode IAFC/fVIF fVIFacc(dig) fVIFacc(a) AFC radio mode IAFC/fRIF fRIFacc(dig) fRIFacc(a) change of AFC current with RIF frequency digital accuracy of RIF frequency analog accuracy of RIF frequency upper saturation voltage lower saturation voltage maximum output current output resistance voltage gain voltage ratio: pin PORT1 to internal VIF AGC voltage voltage ratio: pin PORT3 to internal TAGC voltage VI
TDA9897_TDA9898_4
Min
[17]
Typ
Max
Unit
AGC monitor (voltage output)
[18][19]
6 6 6 0
-
dB dB dB dB
80 160 160
[19]
200 1.05 -
160 240 240 1.25 +20 +20
A A A A/kHz kHz kHz
change of AFC current with VIF frequency digital accuracy of VIF frequency analog accuracy of VIF frequency read-out via I2C-bus; R1[4:1] = f0; fref = 4 MHz IAFC = 0 A; fref = 4 MHz
0.85 -20 -20
[20]
[20]
[19]
0.85 -10 -10
1.05 -
1.25 +10 +10
A/kHz kHz kHz
read-out via I2C-bus; R1[4:1] = f0; fref = 4 MHz IAFC = 0 A; fref = 4 MHz
[20]
[20]
Pin PORT1 or pin PORT3 operating as voltage monitor Vsat(u) Vsat(l) Io(max) RO Gv VP - 0.8 VP - 0.5 sink or source
[3] [3] [3][17]
0.8 3 -
V V A k dB
0.5 1.3 6
10 -
[3][17]
-
0
-
dB
SIF amplifier; pins IF1A and IF1B or pins IF2A and IF2B or pins IF3A and IF3B input voltage
Rev. 04 -- 25 May 2009
-
1.95
-
V
49 of 103
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol Ri(dif) Ci(dif) Vi(SIF)(RMS) Parameter differential input resistance differential input capacitance RMS SIF input voltage FM mode; -3 dB at intercarrier output pins OUT1A and OUT1B; without FM AGC; see Table 21 AM mode; -3 dB at AF output pin AUD FM mode; +1 dB at intercarrier output pins OUT1A and OUT1B; without FM AGC; see Table 21 AM mode; +1 dB at AF output pin AUD permissible overload GSIF(cr) f-3dB(SIF)l f-3dB(SIF)u tresp control range SIF gain lower SIF cut-off frequency upper SIF cut-off frequency response time increasing or decreasing SIF step of 20 dB; AM mode; fast AGC increasing decreasing increasing or decreasing SIF step of 20 dB; AM mode; slow AGC increasing decreasing increasing or decreasing SIF step of 20 dB; FM mode; normal AGC increasing decreasing increasing or decreasing SIF step of 20 dB; FM mode; fast AGC increasing decreasing
TDA9897_TDA9898_4
Conditions
Min -
Typ 2 3 60
Max 100
Unit k pF V
150
40 190
70 -
V mV
70 60 -
140 66 7 80
320 -
mV mV dB MHz MHz
FM and AM mode
SIF AGC detector; pin MPP; see Figure 16
-
8 10
-
ms ms
-
65 125
-
ms ms
-
0.09 28
-
ms ms
-
0.03 4
-
ms ms
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
50 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol VAGC(SIF) Parameter SIF AGC voltage Conditions FM mode VSIF = 100 V VSIF = 10 mV VSIF = 140 mV AM mode VSIF = 100 V VSIF = 10 mV VSIF = 70 mV Conversion synthesizer PLL; pin LFSYN2 (radio mode) VLFSYN2 KO KD voltage on pin LFSYN2 VCO steepness phase detector steepness fVCO / VLFSYN2 ILFSYN2 / VCO; see Table 57; fVCO selection: 22 MHz to 29.5 MHz 30 MHz to 37.5 MHz 38 MHz to 45.5 MHz 46 MHz to 53.5 MHz 57 MHz Io(PD) phase detector output current sink or source; fVCO selection: 22 MHz to 29.5 MHz 30 MHz to 37.5 MHz 38 MHz to 45.5 MHz 46 MHz to 53.5 MHz 57 MHz n(synth) synthesizer phase noise with 4 MHz crystal oscillator reference; fsynth = 31 MHz; fIF = 36 MHz at 1 kHz at 10 kHz at 100 kHz at 1.4 MHz sp IL spurious suppression leakage current multiple of f = 500 kHz synthesizer spurious performance > 50 dBc
[3] [3] [3] [3] [3] [3]
Min 1.2 2.4 3.1 1.4 2.6 3.2 1 -
Typ 31
Max 2.1 3.2 VP 2.3 3.4 VP 3 -
Unit V V V V V V V MHz/V
-
32 38 47 61 61
-
A/rad A/rad A/rad A/rad A/rad
-
200 238 294 384 384
-
A A A A A
89 89 98 115 50 -
99 99 102 119 -
10
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc nA
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
51 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol PSRR Parameter power supply ripple rejection Conditions residual spurious at nominal differential output voltage dependent on power supply ripple at 70 Hz; see Figure 11 Min Typ 50 Max Unit dB
Single reference QSS intercarrier mixer; pins OUT1A and OUT1B VOUT1A VOUT1B Ibias(int) Isink(o)(max) Isource(o)(max) RO voltage on pin OUT1A (DC) voltage on pin OUT1B (DC) internal bias current (DC) maximum output sink current maximum output source current output resistance for emitter-follower DC and AC DC and AC; with external resistor to GND output active; single-ended to GND output inactive; internal resistance to GND Vo(RMS) RMS output voltage IF intercarrier single-ended to GND; B/G standard; SC1 on; SC2 off; see Figure 9 and Table 21 internal BP via FM AGC internal BP IF intercarrier single-ended to GND; L standard; without modulation; see Figure 9 and Table 21 W7[5] = 0; internal BP + 6 dB W7[5] = 1; internal BP + 6 dB W7[5] = 0; internal BP W7[5] = 1; internal BP f-3dB(ic)u image Vinterf(RMS) upper intercarrier cut-off frequency image rejection RMS interference voltage internal sound band-pass off band-pass off; -8 MHz to 0 MHz fundamental wave and harmonics 90 45 45 20 11 24 140 70 70 35 15 28 2 180 90 90 45 5 mV mV mV mV MHz dB mV 90 90 140 170 180 230 mV mV 1.8 1.8 2.0 1.4 3.0 2.0 2.0 2.5 1.7 800 2.2 2.2 25 V V mA mA mA
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
52 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol G Parameter gain Conditions IF intercarrier; L standard; without modulation QSS mode; BP selection for standard M/N B/G I D/K L/L-accent radio mode; BP selection for standard M/N B/G I D/K f-3dB(BP)u f-3dB(BP)l stpb CC upper BP cut-off frequency lower BP cut-off frequency stop-band attenuation color carrier attenuation QSS mode; BP selection for standard M/N; fCC = 3.58 MHz B/G; fCC = 4.43 MHz I; fCC = 4.43 MHz D/K; fCC = 4.28 MHz L/L-accent; fCC = 4.28 MHz External filter output; pin EXTFILO VEXTFILO VEXTFILO(p-p) voltage on pin EXTFILO (DC) peak-to-peak voltage on pin EXTFILO IF intercarrier; SC1 on; SC2 off IF intercarrier; L standard; without modulation W7[5] = 0 W7[5] = 1 Io(max) maximum output current AC and DC 210 105 1 310 155 410 205 mV mV mA 1.8 420 2.0 620 2.2 820 V mV 15 22 20 20 20 23 30 28 28 28 dB dB dB dB dB fc + 0.5 fc - 0.5 20 4.7 5.75 6.25 6.25 fc + 0.65 fc - 0.65 30 fc + 0.8 fc - 0.8 MHz MHz MHz MHz MHz MHz dB 4.7 5.75 6.25 6.25 6.05 MHz MHz MHz MHz MHz Min Typ 5 Max Unit dB AM intercarrier from pin EXTFILI to pins OUT1A and OUT1B
Band-pass mode fc center frequency
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
53 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol fFMPLL Parameter FM PLL frequency Conditions see Table 18 and Table 20 Min FM PLL filter; pin LFFM VLFFM voltage on pin LFFM fFMPLL = 4.5 MHz fFMPLL = 5.5 MHz fFMPLL = 6.0 MHz fFMPLL = 6.5 MHz fFMPLL = 10.7 MHz Tcy(dah) tw(dah) Io(dah) digital acquisition help cycle time digital acquisition help pulse width digital acquisition help output current sink or source W3[4] = 0; W6[3] = 0; FM window width = 237.5 kHz W3[4] = 1; W6[3] = 0; FM window width = 475 kHz W3[4] = 0; W6[3] = 1; FM window width = 1 MHz W3[4] = 1; W6[3] = 1; FM window width = 1 MHz KD(FM) FM phase detector steepness IFMPLL / VCO(FM) W3[4] = 0; W6[3] = 0; FM window width = 237.5 kHz W3[4] = 1; W6[3] = 0; FM window width = 475 kHz W3[4] = 0; W6[3] = 1; FM window width = 1 MHz W3[4] = 1; W6[3] = 1; FM window width = 1 MHz
TDA9897_TDA9898_4
Typ 4.5 5.5 6.0 6.5 10.7 1.9 2.2 2.35 2.5 2.3 64 16
Max 3.3 3.3 3.3 3.3 3.3 -
Unit MHz MHz MHz MHz MHz V V V V V s s
FM PLL demodulator
1.5 1.5 1.5 1.5 1.5 -
14
18
22
A
28
36
44
A
14
18
22
A
28
36
44
A
-
5.5
-
A/rad
-
14.5
-
A/rad
-
5.5
-
A/rad
-
14.5
-
A/rad
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
54 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol KO(FM) Parameter FM VCO steepness Conditions fFMPLL / VLFFM f < 10 MHz f = 10.7 MHz Ioffset(FM) FM offset current W6[3] = 0; W3[4] = 0 W6[3] = 0; W3[4] = 1 FM intercarrier input; pins EXTFMI and EXTFILI; see Figure 9 |Zi| Vi(FM)(RMS) input impedance RMS FM input voltage AC-coupled via 4 pF gain controlled operation; W1[1:0] = 10 or W1[1:0] = 11 or W1[1:0] = 01 W1[1:0] = 10 or W1[1:0] = 11 or W1[1:0] = 01 W1[1:0] = 10 or W1[1:0] = 11 or W1[1:0] = 01 QSS mode; 25 kHz FM deviation; 75 s de-emphasis QSS mode; 27 kHz FM deviation; 50 s de-emphasis QSS mode; 55 kHz FM deviation; 50 s de-emphasis radio mode; 22.5 kHz FM deviation; 75 s de-emphasis Vo(AF)/T THD AF output voltage variation with temperature total harmonic distortion 50 s de-emphasis; FM deviation: for TV mode 27 kHz and for radio mode 22.5 kHz 2 20 300 k mV -1.5 -2.5 3.3 5.9 0 0 +1.5 +2.5 MHz/V MHz/V A A Min Typ Max Unit
Vlock(min)(RMS)
RMS minimum lock-in voltage RMS minimum FM carrier detection voltage
-
-
1.5
mV
Vdet(FM)min(RMS)
-
-
1.8
mV
FM demodulator part; audio output; pin AUD Vo(AF)(RMS) RMS AF output voltage 400 500 600 mV
430
540
650
mV
900
-
1300
mV
360
450
540
mV
-
1.1 x 10-3 7 x 10-3 dB/K 0.15 0.50 %
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
55 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol fAF(max) Parameter maximum AF frequency deviation Conditions THD < 2 %; pre-emphasis off; fAF = 400 Hz W3[1:0] = 00 (audio gain = 0 dB) W3[1:0] = 01 (audio gain = -6 dB) W3[1:0] = 10 (audio gain = -12 dB) W3[1:0] = 11 (audio gain = -18 dB) and W3[4] = 1 (FM window width = 475 kHz) fAF(max) maximum AF frequency THD < 2 %; pre-emphasis off FM window width = 237.5 kHz; -6 dB audio gain; FM deviation 100 kHz FM window width = 475 kHz; -18 dB audio gain; FM deviation 300 kHz f-3dB(AF) AF cut-off frequency W3[2] = 0; W3[4] = 0; without de-emphasis; FM window width = 237.5 kHz 27 kHz FM deviation; 50 s de-emphasis; vision carrier unmodulated; FM PLL only; "ITU-R BS.468-4" radio mode (10.7 MHz); 22.5 kHz FM deviation; 75 s de-emphasis
[3] [21]
Min
Typ
Max
Unit
55 110 170 380
-
-
kHz kHz kHz kHz
15
-
-
kHz
15
-
-
kHz
80
100
-
kHz
(S/N)w(AF)
AF weighted signal-to-noise ratio
48
56
-
dB
(S/N)unw(AF)
AF unweighted signal-to-noise ratio
-
58
-
dB
VSC(rsd)(RMS)
RMS residual sound carrier fundamental wave and voltage harmonics; without de-emphasis AM suppression referenced to 27 kHz FM deviation; 50 s de-emphasis; AM: f = 1 kHz; m = 54 % fripple = 70 Hz; see Figure 11
-
-
2
mV
AM
35
46
-
dB
PSRR
power supply ripple rejection
14
20
-
dB
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
56 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol Audio amplifier Audio output; pin AUD RO VO RL CL Vo(AF)(RMS) output resistance output voltage load resistance load capacitance RMS AF output voltage 25 kHz FM deviation; 75 s de-emphasis; see Table 27 0 dB -6 dB -12 dB -18 dB AM; m = 54 %; see Table 27 0 dB -6 dB f-3dB(AF)u f-3dB(AF)l mute Vjmp upper AF cut-off frequency lower AF cut-off frequency mute attenuation jump voltage difference (DC) W3[2] = 0 (without de-emphasis) W3[2] = 0 (without de-emphasis) of AF signal switching AF output to mute state or vice versa; activated by digital acquisition help W3[6] = 1 or via W3[5] fripple = 70 Hz; see Figure 11
[22] [3]
Parameter
Conditions
Min
Typ
Max
Unit
2.0 10 100 -
2.4 -
300 2.7 1
V k k nF
AC-coupled DC-coupled
[3] [3] [3]
400 -
500 250 125 62.5
600 -
mV mV mV mV
400 70 -
500 250 150 20 50
600 150
mV mV kHz Hz dB mV
[23]
PSRR
power supply ripple rejection output voltage output resistance
14
20
-
dB
De-emphasis network; pin CDEEM VO RO W3[3:2] = 11 (50 s de-emphasis) W3[3:2] = 01 (75 s de-emphasis) VAF(RMS) RMS AF voltage fAF = 400 Hz; Vo(AF) = 500 mV (RMS); 0 dB attenuation 8.5 13 2.4 170 14 21 V k k mV
TDA9897_TDA9898_4
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Product data sheet
Rev. 04 -- 25 May 2009
57 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol AF decoupling Parameter Conditions Min Typ Max Unit
Pin CAF
Vdec decoupling voltage (DC) fFMPLL = 4.5 MHz fFMPLL = 5.5 MHz fFMPLL = 6.0 MHz fFMPLL = 6.5 MHz fFMPLL = 10.7 MHz IL Io(max) FM leakage current maximum output current VAUD < 50 mV (p-p); 0 dB attenuation sink or source 1.5 1.5 1.5 1.5 1.5 1.15 1.9 2.2 2.35 2.5 2.3 1.5 3.3 3.3 3.3 3.3 3.3 25 1.85 V V V V V nA A
operation[24][25] first sound carrier weighted PC / SC1 > 40 dB at signal-to-noise ratio pins IF1A and IF1B or IF2A and IF2B; 27 kHz FM deviation; BP off; "ITU-R BS.468-4" black picture white picture 6 kHz sine wave (black-to-white modulation) 250 kHz square wave (black-to-white modulation) 45 45 43 50 50 47 dB dB dB
Single reference QSS AF performance; pin AUD[26] (S/N)w(SC1)
45
50
-
dB
TDA9897_TDA9898_4
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Product data sheet
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58 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol (S/N)w(SC1) Parameter Conditions Min Typ Max Unit Single reference QSS AF performance with external FM demodulator connected to OUT1A and first sound carrier weighted PC / SC1 > 40 dB at signal-to-noise ratio pins IF1A and IF1B or IF2A and IF2B; 27 kHz FM deviation; BP off; "ITU-R BS.468-4" black picture white picture 6 kHz sine wave (black-to-white modulation) 250 kHz square wave (black-to-white modulation) sound carrier subharmonics; f = 2.75 MHz 3 kHz sound carrier subharmonics; f = 2.87 MHz 3 kHz (S/N)w(SC2) second sound carrier weighted signal-to-noise ratio with external reference FM demodulator; PC / SC2 > 40 dB at pins IF1A and IF1B or IF2A and IF2B; 27 kHz (54 % FM deviation); BP off; "ITU-R BS.468-4" black picture white picture 6 kHz sine wave (black-to-white modulation) 250 kHz square wave (black-to-white modulation) sound carrier subharmonics; f = 2.75 MHz 3 kHz sound carrier subharmonics; f = 2.87 MHz 3 kHz AM operation L standard; pin AUD Vo(AF)(RMS)
TDA9897_TDA9898_4
OUT1B[27]
53 50 44
58 53 48
-
dB dB dB
40
45
-
dB
45
51
-
dB
46
52
-
dB
48 46 42
55 51 46
-
dB dB dB
29
34
-
dB
44
50
-
dB
45
51
-
dB
RMS AF output voltage
54 % modulation
400
500
600
mV
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
59 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol THD BAF(-3dB) (S/N)w(AF) Parameter total harmonic distortion -3 dB AF bandwidth AF weighted signal-to-noise ratio Conditions 54 % modulation; BP on; see Figure 33 Min 12 Typ 0.5 18 42 50 40 Max 1.0 Unit % kHz dB dB dB
"ITU-R BS.468-4"
BP on BP off composite IF; PC / SC = 10 dB; VIF modulation = color bar; "ITU-R BS.468-4"; SAW filter application see Figure 47; BP on 38 44 -
Reference frequency General fref VOPTXTAL Ri Rrsn(xtal) Cpull Rswoff(OPTXTAL) reference frequency voltage on pin OPTXTAL (DC) input resistance crystal resonance resistance pull capacitance switch-off resistance on pin to switch off crystal input OPTXTAL by external resistor wired between pin OPTXTAL and GND switch-off current Rswoff(OPTXTAL) = 0.22 k Rswoff(OPTXTAL) = 3.3 k Reference frequency input from external source; pin OPTXTAL VOPTXTAL Ri Vref(RMS) RO Cdec voltage on pin OPTXTAL (DC) input resistance RMS reference voltage output resistance decoupling capacitance of external reference signal source to external reference signal source pin open-circuit
[3] [28] [3] [29] [28]
2.3
4 2.6 2 -
2.9 200 4.7
MHz V k pF k
Reference frequency generation with crystal; pin OPTXTAL pin open-circuit
[3]
0.22
Iswoff
2.3
[3]
500 2.6 2 2 100
5000 2.9 400 4.7 -
A A V k mV k pF
pin open-circuit
80 22
[3]
Reference frequency input from external source; pin FREF VFREF Ri fref
TDA9897_TDA9898_4
voltage on pin FREF (DC) input resistance reference frequency
2.2 50 -
2.5 4
2.8 -
V k MHz
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Product data sheet
Rev. 04 -- 25 May 2009
60 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol Vref(RMS) RO Cdec Rswoff(FREF) Parameter RMS reference voltage output resistance decoupling capacitance switch-off resistance on pin FREF Conditions see Figure 34 of external reference signal source; AC-coupled to external reference signal source to switch off reference signal input by external resistor wired between pin FREF and GND Rswoff(FREF) = 3.9 k Rswoff(FREF) = 22 k Group delay select; pin GDS; see Figure 24 and Table 50 VGDS Isink(I) Isource(I) VI voltage on pin GDS input sink current input source current input voltage pin open-circuit pin connected to VP pin connected to GND GDEQ on; W11[2] = 0; pin connected to GND GDEQ on; W11[2] = 1; pin open-circuit GDEQ off; W11[2] = 1; pin connected to GND GDEQ off; W11[2] = 0; pin open-circuit I2C-bus transceiver[30] Address select; pin ADRSEL VADRSEL voltage on pin ADRSEL (DC) pin open-circuit for address select MAD1; pin connected to GND MAD3; pin connected to GND via RADRSEL MAD4; pin connected to VP via RADRSEL MAD2; pin connected to VP Ri RADRSEL I2C-bus VBVS Isink(I) Isource(I)
TDA9897_TDA9898_4
Min 15 22 3.9
Typ 150 100 -
Max 500 4.7 27
Unit mV k pF k
Iswoff
switch-off current
0 0.58VP 0 0.58VP
25 VP -
100 1 72 0.46VP VP 0.46VP VP
A A V A A V V V V
0 0.20VP 0.66VP 0.96VP
[3]
0.5VP 31 47 0.52VP -
0.04VP 0.34VP 0.80VP VP 51.7 10 60
V V V V V k k V A A
61 of 103
input resistance resistance on pin ADRSEL voltage on pin BVS (DC) input sink current input source current pin open-circuit pin connected to VP pin connected to GND
Rev. 04 -- 25 May 2009
42.3 -
voltage select; pin BVS
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified. Symbol VI Parameter input voltage Conditions VCC(I2C-bus) = 5.0 V; pin connected to VP VCC(I2C-bus) = 3.3 V; pin open-circuit VCC(I2C-bus) = 2.5 V; pin connected to GND I2C-bus transceiver; pins SCL and SDA[31] VIH HIGH-level input voltage VCC(I2C-bus) = 5.0 V VCC(I2C-bus) = 3.3 V VCC(I2C-bus) = 2.5 V VIL LOW-level input voltage VCC(I2C-bus) = 5.0 V VCC(I2C-bus) = 3.3 V VCC(I2C-bus) = 2.5 V IIH IIL VOL fSCL VOL Isink(o) HIGH-level input current LOW-level input current LOW-level output voltage SCL clock frequency LOW-level output voltage output sink current I = 2 mA (sink) PORT1 W7[3] = 0 W7[3] = 1 PORT2; W8[7] = 1 W8[1] = 0 W8[1] = 1 PORT3; W8[7] = 1 W8[2] = 0 W8[2] = 1 VOH
[1] [2] [3] [4]
[32] [33] [33] [32] [33] [33]
Min 0.88VP 0.46VP 0
Typ -
Max VP 0.58VP 0.12VP
Unit V V V
0.6VP 2.3 1.75 -0.3 -0.3 -0.3 -10 -10
-
VP VP VP +0.3VP +1.0 +0.75 +10 +10 0.4 400 0.4 3 10 3 10 3 10
V V V V V V A A V kHz V mA A mA A mA A
IOL = 3 mA; for data transmission (SDA)
0 -
Pins PORT1 or PORT2 or PORT3 operating as open-collector output port
HIGH-level output voltage
VP + 0.5 V
Values of video and sound parameters can be decreased at VP = 4.5 V. Condition for secure POR is a rise or fall time greater than 2 s. This parameter is not tested during the production and is only given as application information for designing the receiver circuit. Level headroom for input level jumps during gain control setting.
TDA9897_TDA9898_4
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Product data sheet
Rev. 04 -- 25 May 2009
62 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
[5]
BLF(-3dB) = 100 kHz (damping factor d = 1.7; calculated with sync level within gain control range). Calculation of the VIF PLL filter by using the following formulae:
B LF ( -3dB ) = K O K D R , valid for d 1.2 1 d = -- R 2K O K D C 2
with the following parameters: KO = VCO steepness (Hz/V), KD = phase detector steepness (A/rad), R = loop filter serial resistor (), C = loop filter serial capacitor (F), BLF(-3dB) = -3 dB LF bandwidth (Hz), d = damping factor. [6] [7] [8] [9] The VCO frequency offset related to the PC frequency is set to 1 MHz with white picture video modulation. AC load; CL < 20 pF and RL > 1 k. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound carrier traps. Condition: luminance range (5 steps) from 0 % to 100 %. Measurement value is based on 4 of 5 steps. Measurement using 200 kHz high-pass filter, 5 MHz low-pass filter and subcarrier notch filter ("ITU-T J.64").
[10] Modulation VSB; sound carrier off; fvideo > 0.5 MHz. [11] Sound carrier on; fvideo = 10 kHz to 10 MHz. [12] The sound carrier trap can be bypassed by setting the I2C-bus bit W2[0] to logic 0; see Table 23. In this way the full composite video spectrum appears at pin CVBS. The video amplitude is reduced to 1.1 V (p-p). [13] Measurement condition: with transformer, transmitter pre-correction on; reference is at 1 MHz. [14] The response time is valid for a VIF input level range from 200 V to 70 mV. [15] AGC response time increased if no AGC event occurs during two lines at minimum. [16] AGC response time increased if video level falls below half of selected level. [17] Load applied to output pin causes signal loss. The resulting gain can be calculated by using G v(load) = G v + 20 log ------------------- . R + R -
O L
RL
[18] See Figure 19 to smooth current pulses. [19] To match the AFC output signal to different tuning systems a current output is provided. The test circuit is given in Figure 19. The AFC steepness can be changed by different applications of resistors R1 and R2. [20] The AFC value of the VIF and RIF frequency is generated by using digital counting methods. The used counter resolution is provided with an uncertainty of 1 bit corresponding to 25 kHz. This uncertainty of 25 kHz has to be added to the frequency accuracy parameter. [21] Measured with an FM deviation of 25 kHz and the typical AF output voltage of 500 mV (RMS). The audio signal processing stage provides headroom of 6 dB with THD < 1.5 %. The I2C-bus bits W3[0] and W3[1] control the AF output signal amplitude from 0 dB to -18 dB in steps of -6 dB. Reducing the audio gain for handling a frequency deviation of more than 55 kHz avoids AF output signal clipping. [22] Amplitude response depends on dimensioning of FM PLL loop filter. [23] The lower AF cut-off frequency depends on the value of the capacitor at pin CAF. A value of CAF1 = 470 nF leads to f-3dB(AF)l 20 Hz and CAF1 = 220 nF leads to f-3dB(AF)l 40 Hz. [24] For all signal-to-noise measurements the used VIF modulator has to meet the following specifications: a) Incidental phase modulation for black-to-white jump less than 0.5 degrees. b) QSS AF performance, measured with the television demodulator AMF2 (audio output, weighted signal-to-noise ratio) better than 60 dB (at deviation 27 kHz) for 6 kHz sine wave black-to-white video modulation. c) Picture-to-sound carrier ratio PC / SC1 = 13 dB (transmitter). [25] The PC / SC ratio is calculated as the addition of TV transmitter PC / SC1 ratio and SAW filter PC / SC1 ratio. This PC / SC ratio is necessary to achieve the weighted signal-to-noise values as noted. A different PC / SC ratio will change these values. [26] Measurement condition is SC1 / SC2 7 dB. [27] The differential QSS signal output on pins OUT1A and OUT1B is analyzed by a test demodulator TDA9820. The signal-to-noise ratio of this device is better than 60 dB. The measurement is related to an FM deviation of 27 kHz and in accordance with "ITU-R BS.468-4".
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
63 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
[28] The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum FM deviation, sound trap frequency, LIF band-pass cut-off frequency, as well as the accuracy of the synthesizer. [29] The value of Cpull determines the accuracy of the resonance frequency of the crystal. It depends on the used type of crystal. [30] The AC characteristics are in accordance with the I2C-bus specification for fast mode (maximum clock frequency is 400 kHz). Information about the I2C-bus can be found in the brochure "The I2C-bus and how to use it" (order number 9398 393 40011). [31] The SDA and SCL lines will not be pulled down if VP is switched off. [32] The threshold is dependent on VP. [33] The threshold is independent of VP.
Table 54. 200 410 110 210 Table 55. Symbol fPC fSC1 fSC2
Examples to the FM PLL filter Cs (nF) 2.2 2.2 2.2 2.2 Cpar (pF) 100 47 470 47 Rs (k) 8.2 5.6 5.6 8.2 Comment recommended for single-carrier-sound, FM narrow recommended for single-carrier-sound, FM wide recommended for two-carrier-sound, FM narrow used for test circuit
BLF(-3dB) (kHz)
Input frequencies and carrier ratios (examples) Parameter picture carrier frequency sound carrier frequency 1 sound carrier frequency 2 B/G standard M/N standard L standard L-accent standard 38.375 32.825 32.583 13 20 38.375 33.825 7 38.375 31.825 10 33.625 40.125 10 Unit MHz MHz MHz dB dB
PC / SC1 picture to first sound carrier ratio PC / SC2 picture to second sound carrier ratio
trap bypass mode normal mode 1.7 V normal mode 2.0 V 2.72 V 2.6 V 3.08 V 2.9 V 3.41 V 3.20 V zero carrier level white level
1.83 V
1.71 V
1.80 V
black level
1.5 V
1.2 V
1.20 V
sync level
001aaj651
Fig 10. Typical video signal levels on output pin CVBS (sound carrier off)
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
64 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
V = VP + Vripple
TDA9897 TDA9898
VP (V) 5.050 5.000 4.950
t (s)
001aae391
Fig 11. Ripple rejection condition
5 Vmonitor(VIFAGC) (V) 4
001aaj590
5 VTAGC (V) 4
3
3
2
(1) (2) (3) (4)
2
1
1
0 30 50 70 90
0 110 130 Vi(VIF) (dBV)
(1) VIF AGC. (2) TAGC; W10 = 00h. (3) TAGC; W10 = 10h. (4) TAGC; W10 = 1Fh.
Fig 12. Typical VIF monitor and TAGC characteristic
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
65 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
100 Vi(IF) (dBV) 90
001aaj591
80
70
60
Fig 13. Typical tuner takeover point as a function of I2C-bus register W9 or W10
(1) IF based TAGC (TOP2).
Fig 14. Typical tuner takeover point as a function of resistor RTOP2
TDA9897_TDA9898_4
Product data sheet
0 0000 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111 0 1000 0 1001 0 1010 0 1011 0 1100 0 1101 0 1110 0 1111 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1 1011 1 1100 1 1101 1 1110 1 1111 Integral TAGC (W9); step width: 1.255 dB typical. IF based TAGC (W10). bit pattern W9[4:0] or W10[4:0] 100 Vi(IF) (dBV) 90
001aaj592
50
80
(1)
70
60
50 0 5 10 15 20 25 RTOP2 (k)
(c) NXP B.V. 2009. All rights reserved.
Rev. 04 -- 25 May 2009
66 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
5 VAGC(FM) (V) 4
001aaj593
5 VAGC(SIF) (V) 4
001aaj594
3
3
2
2
(1) (2)
1
1
0 40 60 80 100 120 Vi(EXTFMI) (dBV)
0 20 40 60 80 100 120 Vi(SIF) (dBV)
(1) AM. (2) FM.
Fig 15. Typical FM AGC characteristic measured at pin MPP
Fig 16. Typical SIF AGC characteristic measured at pin MPP
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
67 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
250 fAFC(VIF)(5) (kHz) 150
(1)
008aaa035
250 IAFC(6) (A) 150
50 bit AFCWIN (R1[7]) = 1 0 -50
(3) (2)
50 0 -50
-150
(4)
-150
-250 36.375
36.875
37.375
37.875
38.375
38.875
39.375
-250 39.875 40.375 fVIF (MHz)
(1) VIF AFC via I2C-bus; accuracy is 1 digit. (2) Bit AFCWIN via I2C-bus (VCO is in 1.6 MHz window) for all standards except M/N standard. (3) Bit AFCWIN via I2C-bus (VCO is in 0.8 MHz window) for M/N standard. (4) VIF AFC average current. (5) Reading via I2C-bus. (6) Average; RC network at pin MPP.
Fig 17. Typical analog and digital AFC characteristic for VIF
250 fAFC(RIF)(4) (kHz) 150
(1)
001aad443
250 IAFC(5) (A) 150
(2)
50 0 -50
50 0 -50
-150 AFC undefined 5.2 bit CARRDET (R1[5]) = 1 5.4 5.6
(3)
-150 AFC undefined 5.8 fRIF (MHz)
-250 5.0
-250 6.0
Characteristics of digital and analog radio AFC is mirrored with respect to center frequency when lower sideband is used (W2[3] = 0). (1) RIF AFC via I2C-bus. (2) FM carrier detection via I2C-bus. (3) RIF AFC average current. (4) Reading via I2C-bus. (5) Average; RC network at pin MPP.
Fig 18. Typical analog and digital AFC characteristic for RIF
TDA9897_TDA9898_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 May 2009
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
VP
R1 22 k
IAFC MPP
TDA9897 TDA9898
R2 22 k
100 nF
008aaa152
Fig 19. RC network for measurement of analog AFC characteristic
60 S/N (dB) 50
(2)
001aaj595
(1)
40
30
20 50 60 70 80 90 100 Vi(VIF) (dBV)
(1) B/G standard; weighted video S/N; using 50 % grey picture. (2) M/N standard; unweighted video S/N; using 50 IRE grey picture.
Fig 20. Typical signal-to-noise ratio as a function of VIF input voltage
TDA9897_TDA9898_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
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69 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
5 resp(f) 0 (dB) -5 -10 -15 -20 -25 -30 -35 -40 -45 0 1 2 3 4 5
(1) (2) (3)
001aaj556
6 f (MHz)
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap amplitude frequency response.
Fig 21. Typical amplitude frequency response for sound trap at M/N standard (including Korea)
250 200 td(grp) (ns) 150 100 50 0 -50 -100 -150 -200 -250 0 1 2 3 4 5
(1)
001aaj555
(3)
(2)
6 f (MHz)
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap group delay response.
Fig 22. Typical group delay response for sound trap at M/N standard
TDA9897_TDA9898_4
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Product data sheet
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70 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
5 resp(f) 0 (dB) -5 -10 -15 -20 -25 -30 -35 -40 -45 0 1 2 3 4 5 6 7
(1) (3)
001aaj557
(2)
8 f (MHz)
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap amplitude frequency response.
Fig 23. Typical amplitude frequency response for sound trap at B/G standard
250 200 td(grp) (ns) 150 100
(1)
001aaj554
50 0 -50 -100 -150 -200 -250 0 1 2 3 4 5
(2)
(3) (4)
(5)
6 f (MHz)
(1) Minimum requirements upper limit (valid for GDEQ off). (2) Minimum requirements lower limit (valid for GDEQ off). (3) Typical trap group delay response; GDEQ off. (4) Typical trap group delay response; GDEQ on. (5) Typical group delay response of additional group delay equalizer (difference of curves 3 and 4).
Fig 24. Typical group delay response for sound trap at B/G standard
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Multistandard hybrid IF processing
5 resp(f) 0 (dB) -5 -10 -15 -20 -25 -30 -35 -40 -45 0 1 2 3 4 5 6 7
(1) (2) (3)
001aaj553
8 f (MHz)
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap amplitude frequency response.
Fig 25. Typical amplitude frequency response for sound trap at I standard
250 200 td(grp) (ns) 150 100
(1)
001aaj552
50 0 -50 -100 -150 -200 -250 0 1 2 3 4 5 6 7 f (MHz) 8
(3)
(2)
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap group delay response.
Fig 26. Typical group delay response for sound trap at I standard
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Multistandard hybrid IF processing
5 resp(f) 0 (dB) -5 -10 -15 -20 -25 -30 -35 -40 -45 0 1 2 3
001aaj551
(1)
(2)
(3)
4
5
6
7 f (MHz)
8
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap amplitude frequency response.
Fig 27. Typical amplitude frequency response for sound trap at D/K standard
250 200 td(grp) (ns) 150 100 50 0 -50 -100 -150 -200 -250 0 1 2 3 4 5 6 7
(2) (1) (3)
001aaj550
8 f (MHz)
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap group delay response.
Fig 28. Typical group delay response for sound trap at D/K standard
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Multistandard hybrid IF processing
5 resp(f) 0 (dB) -5 -10 -15 -20 -25 -30 -35 -40 -45 0 1 2 3 4 5 6 7
(1) (3)
001aaj549
(2)
8 f (MHz)
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap amplitude frequency response.
Fig 29. Typical amplitude frequency response for sound trap at L standard
250 200 td(grp) (ns) 150 100 50 0 -50 -100 -150 -200 -250 0 1 2 3 4 5 6 7
(1) (3)
001aaj548
(2)
8 f (MHz)
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap group delay response.
Fig 30. Typical group delay response for sound trap at L standard
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Multistandard hybrid IF processing
10 resp(f) (dB) 0
(1) (5) (3) (2) (4)
001aaf579
-10
(7) (6)
-20
-30
-40
-50 -3.0
-2.0
-1.0
0
1.0
2.0
f - fc (MHz)
3.0
(1) Center frequency. (2) Minimum upper cut-off frequency. (3) Minimum lower cut-off frequency. (4) Maximum upper cut-off frequency. (5) Maximum lower cut-off frequency. (6) Minimum upper stop-band attenuation. (7) Minimum lower stop-band attenuation.
Fig 31. Typical sound BP amplitude frequency response at TV mode, normalized to BP center frequency
10 Vo(AF) (dB)
(1)
001aaj633
0
(2) (1)
(2) (3)
-10
-20
(3)
-30 10
102
103
104 fAF (kHz)
105
(1) FM; transmitter pre-correction off and receiver de-emphasis off; FM PLL filter: Rs = 5.6 k and Cpar = 47 pF. (2) AM and AGC normal. (3) AM and AGC fast.
Fig 32. Typical AM and FM audio frequency response
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Multistandard hybrid IF processing
2.0 THD (%) 1.5
001aaj596
1.0
0.5
0 10
102
103
104 fAF (kHz)
105
Fig 33. Typical total harmonic distortion as a function of audio frequency at AM standard
60 (S/N)unw (dB) 50
001aaj597
40
30 0 50 100 150 200 Vi(FREF)(RMS) (mV)
Reference frequency input signal taken from external quartz circuit.
Fig 34. Unweighted FM audio S/N versus reference frequency input level using radio mode
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Multistandard hybrid IF processing
120 antenna input level (dBV) 100
001aaf639
1 IF signal RMS values (V) 10-1
(5) (4)
(2)
(3)
(6)
80
RF gain control range IF gain control range limited by TOP adjustment
10-2 IF gain control range 10-3
60
40
10-4
(1)
20
10-5
(7)
output
output
output
output
tuner TD1716
band-pass X3450L
VIF amplifier
demodulator IF demodulator, TDA989x
video amplifier
Video signal related peak-to-peak levels are divided by factor 22 in order to conform with the RMS value scale of the secondary y-axis, but disregarding the none sine wave signal content. (1) Signal levels for -1 dB video output level using maximum RF gain and maximum IF gain. (2) Signal levels for +1 dB video output level using minimum IF gain. (3) Signal levels for TOP-adjusted tuner output level using maximum RF gain and adjustment-related minimum IF gain. (4) Signal levels for TOP-adjusted tuner output level using minimum RF gain and adjustment-related minimum IF gain. (5) TOP-adjusted tuner output level. (6) TOP-adjusted VIF amplifier input level. (7) Minimum antenna input level at -1 dB video level.
Fig 35. Front-end level diagram
TDA9897_TDA9898_4
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Product data sheet
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output
input
input
input
input
input
0
10-6
77 of 103
NXP Semiconductors
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Multistandard hybrid IF processing
12.2 Digital TV signal processing
Table 56. Characteristics VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol VI Ri(dif) Ci(dif) GIF(cr) VO Ibias(int) Isink(o)(max) Isource(o)(max) RO Parameter input voltage differential input resistance differential input capacitance control range IF gain output voltage internal bias current (DC) maximum output sink current maximum output source current output resistance pin open-circuit for emitter-follower DC and AC; see Figure 36 DC and AC; see Figure 36 differential; output active output inactive; internal resistance to GND Vi(IF)(RMS) RMS IF input voltage minimum input sine wave level for nominal output level maximum input sine wave level for nominal output level permissible overload Direct IF; pins OUT2A and OUT2B GIF(max) Vo(dif)(p-p) maximum IF gain peak-to-peak differential output voltage output peak-to-peak level to input RMS level ratio between pin OUT2A and pin OUT2B W4[7] = 0 W4[7] = 1 C/N carrier-to-noise ratio at fo = 33.4 MHz; see Figure 37 Vi(IF) = 10 mV (RMS) Vi(IF) = 0.5 mV (RMS) IM intermodulation suppression input signals: fi = 47.0 MHz and 57.5 MHz; output signals: fo = 36.5 MHz or 68.0 MHz; see Figure 38 W4[7] = 0 W4[7] = 1
TDA9897_TDA9898_4
Conditions
Min 1.8
[2]
Typ 1.93 2 3 66 2.0 2.5 1.7 800 70 170 83
Max 2.2 2.2 50 100 320 -
Unit V k pF dB V mA mA mA V mV mV dB
IF amplifier; IF1A and IF1B or IF2A and IF2B or pins IF3A and IF3B 60 1.8 2.0
[3]
[2]
[2]
DTV differential output; pins OUT1A, OUT1B, OUT2A and OUT2B
1.4 6.0 130
[3]
[2] [2]
[2]
-
[2]
[4]
[2][5][6]
1.0 0.50
1.1 0.55
V V
115 90
[2]
124 104
-
dBc/Hz dBc/Hz
40 40
-
-
dB dB
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Multistandard hybrid IF processing
Table 56. Characteristics ...continued VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol fIF(-1dB)l f-3dB(IF)u PSRR Parameter lower -1 dB IF cut-off frequency upper IF cut-off frequency power supply ripple rejection W4[7] = 0 W4[7] = 1 residual spurious at nominal differential output voltage dependent on power supply ripple fripple = 70 Hz fripple = 20 kHz Low IF output signal; pins OUT1A and OUT1B; differential GIF(max) fsynth Vo(dif)(p-p) maximum IF gain output peak-to-peak level to input RMS level ratio W4[7] = 0 W4[7] = 1 residual spurious at nominal differential output voltage dependent on power supply ripple fripple = 70 Hz fripple = 20 kHz ripple(pb)LIF low IF pass-band ripple 6 MHz bandwidth 7 MHz bandwidth 8 MHz bandwidth B-3dB -3 dB bandwidth BP off 6 MHz bandwidth 7 MHz bandwidth 8 MHz bandwidth stpb stop-band attenuation 6 MHz band; f = 11.75 MHz 6 MHz band; f = 20 MHz 7 MHz band; f = 13.75 MHz 7 MHz band; f = 20 MHz 8 MHz band; f = 15.75 MHz 8 MHz band; f = 20 MHz
[4] [4] [4] [4] [2]
Conditions
[2]
Min 60 60
Typ 7 -
Max -
Unit MHz MHz MHz
[4] [7] [2]
[4] [4] [2]
60 60 89 2 1
-
dB dB dB MHz V V
synthesizer frequency see Table 34 and Table 35 peak-to-peak differential output voltage power supply ripple rejection
-
PSRR
11 30 28 30 28 30 28
50 30 15 7.8 8.8 9.8 40 35 40 35 40 35
2.7 2.7 2.7 -
dB dB dB dB dB MHz MHz MHz MHz dB dB dB dB dB dB
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Product data sheet
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Multistandard hybrid IF processing
Table 56. Characteristics ...continued VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol td(grp) Parameter group delay time variation Conditions from 1 MHz to 2 MHz from 2 MHz to end of band with a bandwidth of 6 MHz 7 MHz 8 MHz image image rejection -10 MHz to 0 MHz BP on BP off C/N carrier-to-noise ratio at fo = 4.9 MHz; see Figure 37 Vi(IF) = 10 mV (RMS) Vi(IF) = 0.5 mV (RMS) H(ib) in-band harmonics suppression low IF = multiple of 1.31 MHz; fi = fsynth + 1.31 MHz; see Figure 40 W4[7] = 0 W4[7] = 1 IM intermodulation suppression input signals: fi = fsynth + 4.7 MHz and fsynth + 5.3 MHz; output signals: fo = 4.1 MHz or 5.9 MHz; see Figure 39 W4[7] = 0 W4[7] = 1 sp(ib) in-band spurious suppression single-ended AC load; RL = 1 k; CL = 5 pF; 1 MHz to end of band; BP on single-ended AC load; RL = 1 k; CL = 5 pF; BP on
[2] [2] [2] [2][5][6] [2] [2]
Min -
Typ 90
Max 200
Unit ns
30 24
90 90 90 34 28
160 160 160 -
ns ns ns dB dB
112 90
118 104
-
dBc/Hz dBc/Hz
40 40
-
-
dB dB
40 40 50
-
-
dB dB dB
sp(ob)
out-band spurious suppression maximum input sink current maximum input voltage voltage on pin AGCDIN
[2]
50
-
-
dB
IF AGC control; pin AGCDIN Isink(i)(max) Vi(max) VAGCDIN GIF/VAGCDIN
[2]
0 -
-45
2 VP 3 -
A V V dB/V
[2]
[2]
change of IF gain with VAGCDIN = 0.8 V to 2.2 V voltage on pin AGCDIN
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Product data sheet
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Multistandard hybrid IF processing
Table 56. Characteristics ...continued VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Tuner AGC; pin TAGC TAGC integral loop mode (W6[7:6] = 10); TAGC is current output; unmodulated IF; see Table 44 and Figure 13 Vi(IF)(RMS) RMS IF input voltage at starting point of tuner AGC takeover; Isink(TAGC) = 100 A W9[4:0] = 0 0000 W9[4:0] = 1 0000 W9[4:0] = 1 1111 acc(set)TOP Isource TOP setting accuracy source current TAGC charge current normal mode; W9[5] = 0 normal mode; W9[5] = 1 fast mode activated by internal level detector; W9[5] = 0 fast mode activated by internal level detector; W9[5] = 1 Isink sink current TAGC discharge current; VTAGC = 1 V Isink(TAGC) = 100 A; W9[4:0] = 1 0000
[2]
-2 0.20 1.6 7
59.6 78.3 98.5 0.33 2.5 11
+2 0.45 3.4 15
dBV dBV dBV dB A A A
60
90
120
A
375 -
500 0.006
625 0.02
A dB/K
acc(set)TOP/T TOP setting accuracy variation with temperature RL Vsat(u) Vsat(l) th(fast)AGC load resistance upper saturation voltage lower saturation voltage AGC fast mode threshold
[2]
50 VP - 0.3 6
8
0.3 10
M V V dB
pin operating as current output pin operating as current output activated by internal fast AGC detector; I2C-bus setting corresponds to W9[4:0] = 1 0000 before activating; Vi(IF) below th(fast)AGC
[2]
[2]
[2]
td
delay time
[2]
40
60
80
ms
Filter synthesizer PLL; pin LFSYN1 VLFSYN1 KO KD Isink(o)PD(max) voltage on pin LFSYN1 VCO steepness phase detector steepness maximum phase detector output sink current fVCO / VLFSYN1 ILFSYN1 / VCO 1.0 3.75 9 3.5 65 V MHz/V A/rad A
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Product data sheet
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NXP Semiconductors
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Multistandard hybrid IF processing
Table 56. Characteristics ...continued VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol Isource(o)PD(max) Parameter maximum phase detector output source current voltage on pin LFSYN2 VCO steepness phase detector steepness fVCO / VLFSYN2 ILFSYN2 / VCO; see Table 57; fVCO selection: 22 MHz to 29.5 MHz 30 MHz to 37.5 MHz 38 MHz to 45.5 MHz 46 MHz to 53.5 MHz 57 MHz Io(PD) phase detector output sink or source; current fVCO selection: 22 MHz to 29.5 MHz 30 MHz to 37.5 MHz 38 MHz to 45.5 MHz 46 MHz to 53.5 MHz 57 MHz n(synth) synthesizer phase noise fsynth = 31 MHz; fIF = 36 MHz at 1 kHz at 10 kHz at 100 kHz at 1.4 MHz fsynth = 40 MHz; fIF = 44 MHz; external 4 MHz reference signal of 265 mV (RMS) and phase noise better than 120 dBc/Hz; see Figure 46 at 1 kHz at 10 kHz at 100 kHz at 1.4 MHz sp IL spurious suppression leakage current multiple of f = 500 kHz synthesizer spurious performance > 50 dBc
[2] [2] [2] [2] [2] [2] [2] [2] [2] [2]
Conditions
Min -
Typ -
Max 65
Unit A
Conversion synthesizer PLL; pin LFSYN2 VLFSYN2 KO KD 1 31 3 V MHz/V
-
32 38 47 61 61
-
A/rad A/rad A/rad A/rad A/rad
-
200 238 294 384 384
-
A A A A A
89 89 98 115
99 99 102 119
-
dBc/Hz dBc/Hz dBc/Hz dBc/Hz
89 89 96 115 50 -
96 100 100 118 -
10
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc nA
TDA9897_TDA9898_4
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Product data sheet
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82 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 56. Characteristics ...continued VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol General fref VOPTXTAL Ri Rrsn(xtal) Cpull Rswoff(OPTXTAL) reference frequency voltage on pin OPTXTAL (DC) input resistance crystal resonance resistance pull capacitance switch-off resistance on pin OPTXTAL to switch off crystal input by external resistor wired between pin OPTXTAL and GND Rswoff(OPTXTAL) = 0.22 k Rswoff(OPTXTAL) = 3.3 k Reference frequency input from external source; pin OPTXTAL VOPTXTAL Ri Vref(RMS) RO Cdec voltage on pin OPTXTAL (DC) input resistance RMS reference voltage output resistance decoupling capacitance voltage on pin FREF (DC) input resistance reference frequency RMS reference voltage output resistance decoupling capacitance see Figure 46 of external reference signal source; AC-coupled to external reference signal source of external reference signal source to external reference signal source pin open-circuit
[2] [8] [2] [9] [8]
Parameter
Conditions
Min
Typ
Max
Unit
Reference frequency 2.3
[2]
4 2.6 2 -
2.9 200 4.7
MHz V k pF k
Reference frequency generation with crystal; pin OPTXTAL pin open-circuit
0.22
Iswoff
switch-off current
2.3
[2]
500 2.6 2 2 100
5000 2.9 400 4.7 -
A A V k mV k pF
pin open-circuit
80 22
[2]
Reference frequency input from external source; pin FREF VFREF Ri fref Vref(RMS) RO Cdec 2.2 50 15 22 2.5 4 150 100 2.8 500 4.7 V k MHz mV k pF
TDA9897_TDA9898_4
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Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 56. Characteristics ...continued VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol Rswoff(FREF) Parameter switch-off resistance on pin FREF Conditions to switch off reference signal input by external resistor wired between pin FREF and GND Rswoff(FREF) = 3.9 k Rswoff(FREF) = 22 k
[1] [2] [3] [4] [5] [6] [7] [8] [9] Some parameters can be decreased at VP = 4.5 V. This parameter is not tested during production and is only given as application information. Output current can be increased by application of single-ended resistor from each output pin to GND. Recommended resistor value is minimum 1 k. With single-ended load for fIF < 45 MHz RL 1 k and CL 5 pF to ground and for fIF = 45 MHz to 60 MHz RL = 1 k and CL 3 pF to ground. Noise level is measured without input signal but AGC adjusted corresponding to the given input level. Set with AGC nominal output voltage as reference. For C/N measurement switch input signal off. With single-ended load RL 1 k and CL 5 pF to ground. The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum FM deviation, sound trap frequency, LIF band-pass cut-off frequency, as well as the accuracy of the synthesizer. The value of Cpull determines the accuracy of the resonance frequency of the crystal. It depends on the used type of crystal.
Min 3.9
Typ -
Max 27
Unit k
Iswoff
switch-off current
-
25
100 -
A A
Table 57. fVCO (MHz) 22 to 29.5 30 to 37.5 38 to 45.5 46 to 53.5 57
[1]
Conversion synthesizer PLL; loop filter dimensions[1] RLFSYN2 (k)[2] 1.5 1.8 2.2 2.7 3.3 CLFSYN2 (nF) 4.7 4.7 4.7 4.7 4.7
Calculation of the PLL loop filter by using the following formulae:
KO B LF ( -3dB ) = ------ D R LFSYN2 , valid for d 1.2 -K N KO 1 d = -- R LFSYN2 2 ------ D C LFSYN2 -K 2 N
with the following parameters: KO = VCO steepness (Hz/V), N = divider ratio: N = ------------------- , KD = phase detector steepness (A/rad), RLFSYN2 = synthesizer loop filter serial resistor (), CLFSYN2 = synthesizer loop filter serial capacitor (F), BLF(-3dB) = -3 dB LF bandwidth (Hz), d = damping factor. [2] If more than one frequency range is used in the application, then the smallest resistor value should be applied.
(c) NXP B.V. 2009. All rights reserved.
f VCO 0.5 MHz
TDA9897_TDA9898_4
Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
30 CL(dif) (pF) 20
008aaa153
(2)
10
(1)
0 0 1 2 RL(dif) (k) 3
W4[7] = 0; nominal output level (1) Direct IF, fmax = 40 MHz, with single-ended resistors of 1 k to GND. (2) Low IF, fmax = 9 MHz.
Fig 36. Maximum differential load figures at OUT1/OUT2
130 C/N (dBc/Hz) 120
(2) (3) (1)
001aaj598
110
100
90
80 30 50 70 90 110 Vi(IF)(RMS) (dBV)
(1) Direct IF. (2) Low IF. (3) Noise level of measurement setup.
Fig 37. Typical C/N ratio as a function of IF input voltage
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NXP Semiconductors
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Multistandard hybrid IF processing
Vi(IF)(RMS) (dBV) 74
Vo(dif)(p-p) (V) 0.5
(1)
IM
0
0
47
57.5
0 fi (MHz)
0
36.5
47
57.5
68
input signal
output signal
fo (MHz)
008aaa051
(1) 0.25 V for W4[7] = 1.
Fig 38. Direct IF signal conditions for measurement of intermodulation at OUT2
Vi(IF)(RMS) (dBV) 74
Vo(dif)(p-p) (V) 0.5
(1)
IM
0 36 fsynth
40.7
41.3
0 fi (MHz)
0
4.1
4.7
5.3
5.9
input signal
output signal
fo (MHz)
008aaa053
(1) 0.25 V for W4[7] = 1.
Fig 39. Low IF signal conditions for measurement of intermodulation at OUT1
Vi(IF)(RMS) (dBV) 80
Vo(dif)(p-p) (V) 2.0
(1)
H(ib)
0 36 fsynth
37.31 input signal
0 fi (MHz)
0
1.31
2.62
3.93
5.24
6.55
7.86
output signal
fo (MHz)
008aaa054
(1) 1.0 V for W4[7] = 1.
Fig 40. Low IF signal conditions for measurement of harmonics at OUT1
TDA9897_TDA9898_4
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Product data sheet
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NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
resp(f) (dB) 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 0 2 4 6 8 10 12 f (MHz)
(1) (2) (3) (1) (2) (3)
2
001aaj605
td(grp)LIF (ns)
100 0 -100 -200
tolerance scheme:
(1) (2) (3)
(1) Channel bandwidth = 6 MHz. (2) Channel bandwidth = 7 MHz. (3) Channel bandwidth = 8 MHz.
Fig 41. Detailed low IF amplitude and group delay pass-band tolerance scheme
10 resp(f) (dB) 0 -10 -20 -30 -40 -50 -60 -70 -30 -25 -20 -15 -10
001aaj607
(1) (2) (3)
-5
0 f (MHz)
tolerance scheme:
(1) (2) (3)
(1) Channel bandwidth = 6 MHz. (2) Channel bandwidth = 7 MHz. (3) Channel bandwidth = 8 MHz.
Fig 42. Low IF amplitude stop-band tolerance scheme
TDA9897_TDA9898_4
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Product data sheet
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87 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
10 resp(f) (dB) 0 -10 -20 -30 -40 -50 -60 -70
(1) (2) (3)
001aaj606
0
5
10
15
20
25 30 f (MHz)
(3)
tolerance scheme:
(1) (2)
(1) Channel bandwidth = 6 MHz. (2) Channel bandwidth = 7 MHz. (3) Channel bandwidth = 8 MHz.
Fig 43. Low IF amplitude pass-band tolerance scheme
100 G(7) (dB) 80
001aaj599
60
(1) (2) (3)
(4) (5) (6)
40
20
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VAGCDIN (V)
(1) 2.0 V (p-p) differential output voltage (LIF, W9[7] = 0, W4[7] = 0). (2) 1.0 V (p-p) differential output voltage (LIF, W9[7] = 0, W4[7] = 1; DIF, W9[7] = 0, W4[7] = 0). (3) 0.5 V (p-p) differential output voltage (DIF, W9[7] = 0, W4[7] = 1). (4) 2.0 V (p-p) differential output voltage (LIF, W9[7] = 1, W4[7] = 0). (5) 1.0 V (p-p) differential output voltage (LIF, W9[7] = 1, W4[7] = 1; DIF, W9[7] = 1, W4[7] = 0). (6) 0.5 V (p-p) differential output voltage (DIF, W9[7] = 1, W4[7] = 1). (7) Ratio of output peak-to-peak level to input RMS level.
Fig 44. Typical gain characteristic for AGCDIN control voltage
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2.5 VLFSYN2 (V) 2.0
001aaj601
1.5
1.0 20 30 40 50 60 fsynth (MHz)
Fig 45. Typical synthesizer loop filter voltage as function of synthesizer frequency
105 n(synth) (dBc/Hz) 95
(3) (1) (2)
001aaj600
85
75 0 100 200 300 400 500 Vi(FREF)(RMS) (mV)
fsynth = 40 MHz; fIF = 44 MHz; sound BP off (1) f = 100 kHz. (2) f = 10 kHz. (3) f = 1 kHz.
Fig 46. Typical synthesizer phase noise at carrier frequency plus f on LIF output versus input voltage on pin FREF
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13. Application information
tuner AGC output 4 MHz reference input synthesizer trap control loop filter
VP = 5 V
100 nF
CTAGC 220 nF
CFREF 100 pF
L(4) 470 nF
470
analog ground
3.3 k
100 nF
synthesizer downconverter loop filter(2)
RLFSYN2 CLFSYN2
n.c.
22 pF
48 1
47
46
45
44
43
42
41
40
39
38
37 36
AGC input for DIF (from channel decoder)
n.c.
2
35
3
34
1.5 nF
4
CIFAGC(5)
33
2 V CVBS output BVS
5
470 nF
32
6 IF(1) 7 MHz WINDOW 7 SAW X3450L
CCTAGC
31
AUD
TDA9897 TDA9898
30 1st DIF
8
100 nF
29
CAF
9 6 MHz WINDOW 10
28
470 nF
27
11
26
digital LIF or analog 2nd sound IF
12 13 14 15 16 17 18 19 20 21 22 23
25 24
220 nF Cpar 100
Cs
Cde-em 4.7 nF
digital ground ADRSEL
100 100
Rs
VIF PLL loop filter
FM PLL loop filter(3)
external FM input
SDA
SCL
001aai815
(1) Optional single-ended IF input possible. (2) Application depends on synthesizer frequency; see Table 57. (3) Application of FM PLL loop filter; see Table 54. (4) EMI suppression filter for DC, e.g. BLM21RK121SN1 (Murata). (5) Capacitor connected only for TDA9898.
Fig 47. Application diagram of TDA9897 and TDA9898; ATV/DVB-T
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tuner AGC output
4 MHz reference input
VP = 5 V
100 nF
synthesizer trap control loop filter
CTAGC 220 nF
CFREF 100 pF
L(3) 470 nF
470
analog ground
3.3 k
100 nF
synthesizer downconverter loop filter(1)
RLFSYN2 CLFSYN2
n.c.
22 pF
48 1
47
46
45
44
43
42
41
40
39
38
37 36
AGC input for DIF (from channel decoder) PORT2
n.c.
2
35
12 SOUND 11 SAW X3751L 8 6 MHz or 8 MHz WINDOW 7 3 17
CCTAGC CIFAGC(4)
3
34
1.5 nF
4
33
2 V CVBS output BVS
5
470 nF
32
6
31
AUD
2
7
TDA9897 TDA9898
30 1st DIF
8
100 nF
29
CAF
9
28
470 nF
10 PORT2
4.7 k
27
11 PORT1
26
digital LIF or analog 2nd sound IF
IF
4.7 k
12 13 14 15 16 17 18 19 20 21 22 23
25 24
BA277
BA277 4.7 k
4.7 k
4.7 k Cde-em 4.7 nF
220 nF
Cs Cpar
digital ground ADRSEL
100 100
VP
100
Rs
VIF PLL loop filter
FM PLL loop filter(2)
external FM input
SDA
SCL
001aai816
(1) Application depends on synthesizer frequency; see Table 57. (2) Application of FM PLL loop filter; see Table 54. (3) EMI suppression filter for DC, e.g. BLM21RK121SN1 (Murata). (4) Capacitor connected only for TDA9898.
Fig 48. Application diagram of TDA9897 and TDA9898; ATV/DVB-T/DVB-C
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tuner AGC output
4 MHz reference input
VP = 5 V
100 nF
synthesizer trap control loop filter
CTAGC 220 nF
CFREF 100 pF
L(3) 470 nF
470
analog ground
3.3 k
100 nF
synthesizer downconverter loop filter(1)
RLFSYN2 CLFSYN2
n.c.
22 pF
48 1
47
46
45
44
43
42
41
40
39
38
37 36
AGC input for DIF (from channel decoder) PORT2
n.c.
2
35
IF
SAW SIF X7550
3
34
1.5 nF
4 n.c.
33
2 V CVBS output BVS
5
32
SAW VIF M1980 NYQUIST SLOPE
CCTAGC
6
31
AUD
TDA9897
7 30 1st DIF 8 29
CAF
100 nF (5)
9
(4) (5)
28
470 nF
10
27
11 PORT1
26
digital LIF or analog 2nd sound IF
12 13 14 15 16 17 18 19 20 21 22 23
25 24
220 nF Cpar 100
Cs
Cde-em 4.7 nF
digital ground ADRSEL
100 100
Rs
VIF PLL loop filter
FM PLL loop filter(2)
external FM input
SDA
SCL
001aai817
(1) Application depends on synthesizer frequency; see Table 57. (2) Application of FM PLL loop filter; see Table 54. (3) EMI suppression filter for DC, e.g. BLM21RK121SN1 (Murata). (4) Optional. (5) Value depends on application.
Fig 49. Application diagram of TDA9897 using SAW filter with Nyquist slope
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22 k
4 MHz 22 pF
buffered TAGC control voltage output CTAGC
220 nF
46
39
47
42
TDA9897 TDA9898
(1) (2)
TDA9897 TDA9898
VP
VAGC voltage monitor output
(3)
12
TDA9897 TDA9898
VP
VP
4.7 k
4.7 k
4.7 k
PORT3 42 PORT1
(4a)
12
TDA9897 TDA9898
(4b)
TDA9897 35 TDA9898
PORT2
(4c)
TDA9897 TDA9898
VP
47 F
VP
47 F
VP
22 k
TDA9897 33 TDA9898
(5a)
68
1 V CVBS (5b) into 75
TDA9897 33 TDA9898
43
1 V CVBS into 75
TDA9897 TDA9898
(6)
16
AFC voltage output
22 k
220
220
100 nF
R 1 k
R 1 k
30
27
R 1 k
TDA9897 TDA9898
(7a)
1st DIF
(7b)
29
TDA9897 TDA9898
R 1 k
26
digital LIF or analog 2nd sound IF
(8)
15
TDA9897 TDA9898
560
17
BP
560
001aai818
(1) Optional 4 MHz quartz crystal oscillator. (2) Alternative buffered TAGC voltage output. (3) Alternative VIF AGC voltage monitor output. (4) Optional use of (a) PORT1, (b) PORT2 or (c) PORT3. (5) Optional CVBS buffer at setting (a) W6[1] = 0, 2 V CVBS or (b) W6[1] = 1, 1.7 V CVBS. (6) Optional analog AFC voltage output. (7) Optional output current increase at output (a) 1st DIF respectively (b) digital LIF. (8) Optional radio application with external BP.
Fig 50. Optional applications
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14. Test information
tuner AGC output 4 MHz reference input synthesizer trap control loop filter
3.3 k(2) CTAGC 100 nF CFREF 100 pF 22 k(1) 2.7 k(7) 4 MHz(3) 470 100 nF
+5 V
PORT3
VP = 5 V synthesizer downconverter loop filter(4)
RLFSYN2 CLFSYN2
analog ground
22 pF
i.c.
22 pF
n.c. 44 43 42 41 40 39 38 37 36 AGC input for DIF (from channel decoder)
2.7 k(7)
48 1
47
46
45
+5 V n.c. 2 35 PORT2
SIF/DIF
51
1:1
1
5
3
34
1.5 nF
2
3
4
CIFAGC(6)
4
33
2 V CVBS output BVS
5 VIF/SIF/DIF
51 1:1 470 nF
32
1
5
6
31
AUD (b) 1st DIF (a)
CAF
2
3
4
CCTAGC
7
TDA9897 TDA9898
30
8 VIF/SIF/DIF
51 1:1 100 nF
29
1
5
9
28
470 nF
2
3
4
22 k
10
27
(b) (a)
TOP potentiometer for RSSI and positive modulation PORT1 +5 V
11
26
digital LIF or analog 2nd sound IF
2.7 k(7)
12 13 14 15 16 MPP
220 nF Cpar Cs Cde-em 4.7 nF
25 17 18 19 20 21 22 23 24
ADRSEL
digital ground
100
FM PLL loop filter(5) output to sound BPF FM input from sound BPF
Rs
100
100
VIF loop filter
external FM input
SDA
SCL
001aai819
(1) Switch-off resistor connected if external reference signal is not used. (2) Switch-off resistor connected if crystal is not used. (3) Use of crystal is optional. (4) Application depends on synthesizer frequency; see Table 57. (5) Application of FM PLL loop filter; see Table 54. (6) Capacitor connected only for TDA9898. (7) Pull-up resistor connected only for port function.
Fig 51. Test circuit of TDA9897 and TDA9898
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15. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 52. Package outline SOT313-2 (LQFP48)
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HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm
SOT619-1
D
B
A
terminal 1 index area A E A1 c
detail X
e1 e 13 L 12 25 e
1/2 e
C b 24 vMCAB wMC y1 C y
Eh
1/2 e
e2
1 terminal 1 index area 48 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 7.1 6.9 Dh 5.25 4.95 E (1) 7.1 6.9 Eh 5.25 4.95 e 0.5 37
36
X 2.5 scale e1 5.5 e2 5.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT619-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18
Fig 53. Package outline SOT619-1 (HVQFN48)
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16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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16.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 54) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 58 and 59
Table 58. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 59. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 54.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 54. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
17. Soldering of through-hole mount packages
17.1 Introduction to soldering through-hole mount packages
This text gives a very brief insight into wave, dip and manual soldering. Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board.
17.2 Soldering by dipping or by solder wave
Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
17.3 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 C and 400 C, contact may be up to 5 seconds.
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17.4 Package related soldering information
Table 60. Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL PMFP[2]
[1] [2]
Suitability of through-hole mount IC packages for dipping and wave soldering Soldering method Dipping suitable Wave suitable suitable[1] not suitable
For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. For PMFP packages hot bar soldering or manual soldering is suitable.
18. Abbreviations
Table 61. Acronym ADC AFC AGC ATV BP CW DAC DC DIF DSP DTV DVB DVB-C DVB-T EMI ESD FPLL I/O IC IF LCD LIF MAD NB NICAM PLL POR QSS
TDA9897_TDA9898_4
Abbreviations Description Analog-to-Digital Converter Automatic Frequency Control Automatic Gain Control Analog TV Band-Pass Continuous Wave Digital-to-Analog Converter Direct Current Digital Intermediate Frequency Digital Signal Processor Digital TV Digital Video Broadcasting Digital Video Broadcasting-Cable Digital Video Broadcasting-Terrestrial Electro-Magnetic Interference ElectroStatic Discharge Frequency Phase-Locked Loop Input/Output Integrated Circuit Intermediate Frequency Liquid Crystal Display Low Intermediate Frequency Module Address NarrowBand Near Instantaneous Companded Audio Multiplex Phase-Locked Loop Power-On Reset Quasi Split Sound
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Abbreviations ...continued Description Radio Intermediate Frequency Received Signal Strength Indication Surface Acoustic Wave Sound Carrier Sound Intermediate Frequency Tuner Automatic Gain Control TakeOver Point Voltage-Controlled Oscillator Vision Intermediate Frequency Vertical Interval Test Signal
Table 61. Acronym RIF RSSI SAW SC SIF TAGC TOP VCO VIF VITS
19. Revision history
Table 62. Revision history Release date 20090525 Data sheet status Product data sheet Product data sheet Product data sheet Product data sheet Change notice Supersedes TDA9897_TDA9898_3 TDA9897_TDA9898_2 TDA9897_TDA9898_1 Document ID TDA9897_TDA9898_4 Modifications: TDA9897_TDA9898_3 TDA9897_TDA9898_2 TDA9897_TDA9898_1
*
Specification of features for V3 version
20080111 20070411 20060922
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20. Legal information
20.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
20.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Multistandard hybrid IF processing
22. Contents
1 2 2.1 2.2 2.3 2.4 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.4 8.5 8.6 8.7 8.7.1 8.7.2 8.8 8.9 8.10 9 9.1 9.2 9.2.1 9.2.2 10 11 12 12.1 12.2 13 14 15 16 16.1 16.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Analog TV processing. . . . . . . . . . . . . . . . . . . . 1 Digital TV processing . . . . . . . . . . . . . . . . . . . . 2 FM radio mode . . . . . . . . . . . . . . . . . . . . . . . . . 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pinning information . . . . . . . . . . . . . . . . . . . . . 12 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional description . . . . . . . . . . . . . . . . . . 15 IF input switch. . . . . . . . . . . . . . . . . . . . . . . . . 15 VIF demodulator . . . . . . . . . . . . . . . . . . . . . . . 15 VIF AGC and tuner AGC. . . . . . . . . . . . . . . . . 15 Mode selection of VIF AGC . . . . . . . . . . . . . . 15 VIF AGC monitor . . . . . . . . . . . . . . . . . . . . . . 15 Tuner AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DIF/SIF FM and AM sound AGC . . . . . . . . . . 16 Frequency phase-locked loop for VIF . . . . . . . 16 DIF/SIF converter stage . . . . . . . . . . . . . . . . . 17 Mono sound demodulator . . . . . . . . . . . . . . . . 17 FM PLL narrowband demodulation. . . . . . . . . 17 AM sound demodulation . . . . . . . . . . . . . . . . . 17 Audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . 17 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I2C-bus transceiver and slave address . . . . . . 18 2C-bus control . . . . . . . . . . . . . . . . . . . . . . . . . 18 I Read format . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write format . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Subaddress. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Description of data bytes . . . . . . . . . . . . . . . . 24 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 39 Thermal characteristics. . . . . . . . . . . . . . . . . . 39 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 40 Analog TV signal processing . . . . . . . . . . . . . 40 Digital TV signal processing . . . . . . . . . . . . . . 78 Application information. . . . . . . . . . . . . . . . . . 90 Test information . . . . . . . . . . . . . . . . . . . . . . . . 94 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 95 Soldering of SMD packages . . . . . . . . . . . . . . 97 Introduction to soldering . . . . . . . . . . . . . . . . . 97 Wave and reflow soldering . . . . . . . . . . . . . . . 97 16.3 16.4 17 17.1 17.2 17.3 17.4 18 19 20 20.1 20.2 20.3 20.4 21 22 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 97 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 98 Soldering of through-hole mount packages . 99 Introduction to soldering through-hole mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Soldering by dipping or by solder wave . . . . . 99 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 99 Package related soldering information . . . . . 100 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 100 Revision history . . . . . . . . . . . . . . . . . . . . . . 101 Legal information . . . . . . . . . . . . . . . . . . . . . 102 Data sheet status . . . . . . . . . . . . . . . . . . . . . 102 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 102 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 102 Contact information . . . . . . . . . . . . . . . . . . . 102 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 May 2009 Document identifier: TDA9897_TDA9898_4

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